Temperature Dependent Band Gap Correction Model Using Tight-Binding Approach for UTB Device Simulations

Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices

“…where E g (t si , 0) and E g (t si , 300) are the band gap of channel material at 0 K and 300 K, respectively which can be computed using [47] at 0 K and [46] at 300 K. The detailed algorithm to determine β and ∆E T g (t si , T) is provided earlier [45]. The channel electrostatics is obtained using a significant k-points-based approach (termed as RBA), which is shown by Solanki et al [44].…”

“…Furthermore, with a view to maintaining the accuracy as well as reducing the computational cost of calculating the band-structure of ultra-thin-body (UTB) devices from TBM, a significant k-point based approach is recently reported by Solanki et al [44], where identification of significant k-points around the band-minima, enables accurate determination of the electrostatics for DG-SOI MOS devices. Additionally, through the inclusion of a band gap correction term, this significant k-point based approach has been extended from low device temperature to room temperature [45]. Keeping these results as a reference, developing a model that incorporates physical effects such as confinement, due to ultrathin nature of the channel, while the effect of variation of the device temperature is required to be considered to accurately emulate the device electrostatics over a wide range of process and electrical parameters.…”

“…In this work, we firstly briefly discuss how the identification of significant k-points around the band-minima, enables accurate determination of the electrostatics for nanoscale doublegate SOI MOS devices, not just at room temperature, but also at lower device temperatures, through utilization of a suitable band-gap correction model [45]. We then present a model for the electrostatic potential and the electron carrier concentration, in nanoscale double-gate SOI MOS devices, taking the wave nature of the conduction electron into account.…”

“…We then present a model for the electrostatic potential and the electron carrier concentration, in nanoscale double-gate SOI MOS devices, taking the wave nature of the conduction electron into account. This model is extensively benchmarked with the computationally efficient band-structure based electrostatics simulation results [44,45] and shown to be in very good agreement over a wide range of channel thicknesses, device temperatures and gate voltages. From this model, we further show a simplified approach to obtain the channel charge density demonstrating that the channel charge may be modeled as a diffusion layer of uniform potential (along the depth) whose thickness and potential varies with Channel thickness and gate voltage variations.…”

Correlation of Radiation-Induced Interface Traps With Band Edge Energy Through Band Structure-Based Analysis of Electrostatics of UTB SOI Devices

“…Recently, we have shown a methodology to take the effect of interface traps on the electrostatics of Ultra-Thin-Body (UTB) MOS devices by varying the band edge energy (∆E edge ) 13 (which is generally used to passivate the Si-Si0 2 interface 14 ) whereby the position and shape of these interface states within the band gap can be controlled by varying the edge energy at the top/bottom channel/oxide (Si − SiO 2 ) interfaces. By including these interface trap states within the boundary conditions of the self-consistent solution of the 1-D Band structure 15 (along the direction of confinement) and Poisson's equation, the dea) N.V. Mishra and A. S. Medury are with the Department of Electrical Engineering and Computer Science, Indian Institute of Science Education and Research, Bhopal, MP, 462066 India e-mail: nalin20@iiserb.ac.in, adityam@iiserb.ac.in vice electrostatics was determined for UTB DG (Double Gate) MOS devices for a wide range of bias voltages and device temperatures 16 .…”