The accurate calculation of channel electrostatics parameters in ultra-thin body devices requires self-consistent solution of the Poisson's equation and the full-band structure of the thin channel. For silicon channel, the full-band structure is obtained using the semi-empirical sp 3 d 5 s * tight-binding model. To make this approach computationally tractable for a wide range of channel thicknesses, in terms of time and resource, only significant k-points in the irreducible Brillouin zone need to be considered. In this work, we present a scheme for precisely identifying the significant k-points based on Fermi-Dirac probability and show that the band-structure approach using those significant k-points can be applied over a wide range of channel thicknesses, oxide thicknesses, device temperatures and different channel orientations. The benchmarking of the obtained channel electrostatics parameters is performed with the results from accurate full-band structure simulations showing excellent agreement (maximum error within 0.5%) along with significant reduction in computational time.

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Besides being impacted by quantum confinement effects, the channel electrostatics of ultra-thin-body silicon-on-insulator (SOI) MOS devices, with channel thicknesses less than 10 nm, are also likely to be impacted by interface trap states. In this work, we comprehensively investigated the effect of band edge energy (surface passivation energy) on the band structure of the silicon channel. We propose to utilize this band edge energy (ΔEedge) to study the effect of interface traps on device electrostatics, which is generally used to passivate the channel/oxide interface. First, by using sp3d5s∗ semi-empirical tight-binding methodology with a fully passivated interface (ΔEedge>5 eV) and by including suitable bandgap correction for different device temperatures, the band structure is obtained, which is solved self-consistently with Poisson’s equation to accurately determine the channel electrostatics, without the effect of trap states. Interface trap states are now seen in the band structure through suitably varying the edge energy (−5eV<ΔEedge<5 eV) based on which the interface trap density (Dit) and the interface trap charge density (Qit) are determined. Through incorporating Qit in the boundary condition for solving Poisson’s equation self-consistently with the band structure, channel electrostatics is recomputed to analyze the effect of traps for a wide range of device conditions. Finally, the degradation in the integrated charge density due to interface traps is accurately modeled for different SOI channel thickness and device temperatures.

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<div>In Ultra-thin Body (UTB) devices, besides the Ultra-thin (UT) nature of the channel, which manifests in terms of Quantum Confinement Effects (QCEs), the Band-offsets between the oxide and channel materials at their interface, also tends to strongly impact the channel electrostatics. Despite being very accurate in calculating the band-structure and hence considering QCEs for a given channel material, the Tight-Binding (TB) method tends to be more complicated to use at the channel/oxide interface of MOS devices, while on the other hand the Effective Mass Approximation (EMA) in spite of being less accurate, is a simpler approach to consider the effects of band-offsets at the interface. Given its accuracy, we firstly use the $sp^3d^5s^*$ TB method to calculate the Band-structure and then by considering significant k-points, efficiently incorporate the QCE into the electrostatics of Double-Gate (DG) Silicon-on-Insulator (SOI) MOS devices. Considering these results as a reference, with the assumption of an infinite potential well, we propose a modified Effective Mass Approximation (mEMA) approach, whereby introducing energy correction parameters, along with the effective mass parameters, all of which are shown to be gate bias, channel and oxide thickness dependent, the results obtained from the proposed approach are shown to have good agreement with the results from TB method. In order to analyze the effect of Conduction-Band Offset variations on the channel electrostatics parameters, we consider an $SiO_2$ layer of thickness of $1$ $nm$ and show the effect of different Band-offsets on the integrated charge density and gate capacitance, using the mEMA approach.</div><div><br></div>