2016
DOI: 10.1155/2016/6157905
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Temperature Dependent Electrical Transport in Al/Poly(4-vinyl phenol)/p-GaAs Metal-Oxide-Semiconductor by Sol-Gel Spin Coating Method

Abstract: Deposition of poly(4-vinyl phenol) insulator layer is carried out by applying the spin coating technique onto p-type GaAs substrate so as to create Al/poly(4-vinyl phenol)/p-GaAs metal-oxide-semiconductor (MOS) structure. Temperature was set to 80-320 K while the current-voltage (I-V) characteristics of the structure were examined in the study. Ideality factor (n) and barrier height ( ) values found in the experiment ranged from 3.13 and 0.616 eV (320 K) to 11.56 and 0.147 eV (80 K). Comparing the thermionic f… Show more

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Cited by 7 publications
(3 citation statements)
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“…This can be attributed to differences in the affinity of the n-type and p-type Si [30]. Ozden et al fabricated Al/poly(4-vinyl phenol)/p-GaAs metal-oxide-semiconductor and they found ideality factor and barrier height values of 3.13 and 0.616 eV at 320 K and 11.56 and 0.147 eV at 80 K. They concluded that there was an increase in the barrier height as well as a decrease in the ideality factor with increasing temperature [31]. Yuksel et al investigated the temperature-dependent electrical properties of Au/perylene-diimide/n-Si Schottky diodes.…”
Section: Resultsmentioning
confidence: 99%
“…This can be attributed to differences in the affinity of the n-type and p-type Si [30]. Ozden et al fabricated Al/poly(4-vinyl phenol)/p-GaAs metal-oxide-semiconductor and they found ideality factor and barrier height values of 3.13 and 0.616 eV at 320 K and 11.56 and 0.147 eV at 80 K. They concluded that there was an increase in the barrier height as well as a decrease in the ideality factor with increasing temperature [31]. Yuksel et al investigated the temperature-dependent electrical properties of Au/perylene-diimide/n-Si Schottky diodes.…”
Section: Resultsmentioning
confidence: 99%
“…The Si wafers are washed with acetone and isopropanol, followed by mild base piranha wash, and then finally cleaned with plenty of deionized water. [47,48] OFETs (Bottom-gate/top-contact) is fabricated on heavily n + + -doped silicon substrates as a gate electrode (capacitance, C i = 8.3 nF) over which a thermally grown layer of SiO 2 (~300 nm) acts as the gate insulator. The semiconducting films were fabricated using the spin-coating technique.…”
Section: Ofet Characteristicsmentioning
confidence: 99%
“…To explore the OFET characterizations, a Keithley 4200 A semiconductor characterization system was employed. The Si wafers are washed with acetone and isopropanol, followed by mild base piranha wash, and then finally cleaned with plenty of deionized water [47,48] . OFETs (Bottom‐gate/top‐contact) is fabricated on heavily n ++ ‐doped silicon substrates as a gate electrode (capacitance, C i =8.3 nF) over which a thermally grown layer of SiO 2 (∼300 nm) acts as the gate insulator.…”
Section: Ofet Characteristicsmentioning
confidence: 99%