Temperature-dependent low electric field charging of Si nanocrystals embedded within oxide–nitride–oxide dielectric stacks

Abstract

In this work we examine the current peaks and the negative differential resistance that appear in the low electric field regime of oxide-nitride-oxide structures with a two-dimensional band of silicon nanocrystals embedded in a nitride layer. The silicon nanocrystals were synthesized by low energy ion implantation (1 keV, 1.5 x 10(16) Si(+) cm(-2)) and subsequent thermal annealing (950 degrees C, 30 min). Electrical examination was performed at temperatures from 20 to 100 degrees C using constant voltage ramp-rate current measurements. This approach enables us to determine the origin of the observed current peaks as well as to extract the trapping location of the injected carriers within the dielectric stack. The results confirm that the carriers are trapped within the Si nanocrystal band, verifying that this region corresponds to energy minima of the dielectric stack.

Si and Ge nanocrystals for future memory devices

“…This approach enables us to determine the origin of the observed current peaks as well as to extract the trapping location of the injected carriers within the dielectric stack. These results confirm that the carriers are trapped within the Si-NC band, verifying that this region corresponds to energy minima of the dielectric stack [51].…”

Modifications of silicon nitride materials for SONOS memories

“…T related with the state of hydrogen since it is known that high temperat nitride deposition temperature has hydrogen concentration [2]. In our observed V FB positive shift is probab negatively charged defects like th attached hydrogen atom [8]. It is therefore evident that the specific features of the I-V characteristics i.e.…”

“…Once the charge carriers are trapped within the NPs band they create an internal electric field that cancels the increase of the external field leading thus to the appearance of either humps or peaks in the J-E characteristics. A detailed study of the high dose implanted Si-NPs sample was performed by monitoring the current peaks in the lowfield regime by ramp I-V measurements within the temperature range of 22 to 100 o C [8]. Fig.…”

Charge-Trapping Non-Volatile Memories

“…A detailed study of the high-dose implanted Si-NPs sample was performed by monitoring the current peaks in the low-field regime by ramp I-V measurements within the temperature range of 22-100 C (Nikolaou 2009). Figure 3.16 shows room-temperature single sweep I-V measurements performed on the high-dose sample for ramp rates within the 0.1-0.8 V/s range.…”

“…Considering the parallel plate capacitor, an effective thickness, t eff , can be extracted from the C eff values: (Nikolaou et al 2009) where ε ox is the permittivity of the silicon dioxide, ε o the permittivity of vacuum, and A is the area of the gate electrode. The t eff thickness is extracted around 5.8 nm for both electrons and holes.…”