Temperature dependent pulsed IV and RF characterization of β-(AlxGa1−x)2O3/Ga2O3 hetero-structure FET with ex situ passivation

Abstract

In this work, we report a study of the temperature dependent pulsed current voltage and RF characterization of [Formula: see text]-(AlxGa1−x)2O3/Ga2O3 hetero-structure FETs (HFETs) before and after silicon nitride (Si3N4) passivation. Under sub-microsecond pulsing, a moderate DC-RF dispersion (current collapse) is observed before passivation in gate lag measurements, while no current collapse is observed in the drain lag measurements. The dispersion in the gate lag is possibly attributed to interface traps in the gate–drain access region. DC-RF dispersion did not show any strong dependence on the pulse widths. Temperature dependent RF measurements up to 250 °C do not show degradation in the cutoff frequencies. After Si3N4 deposition at 350 °C, a shift of the threshold voltage is observed which changed the DC characteristics. However, the current collapse is eliminated; at 200 ns pulse widths, a 50% higher current is observed compared to the DC at high drain voltages. No current collapse is observed even at higher temperatures. RF performance of the passivated devices does not show degradation. These results show that ex situ deposited Si3N4 is a potential candidate for passivation of [Formula: see text]-(AlxGa1−x)2O3/Ga2O3 HFETs.

Scaled T-Gate β-Ga2O3 MESFETs With 2.45 kV Breakdown and High Switching Figure of Merit

“…Pulsed I-V measurements show very little current collapse as a result of gate bias alone. The lack of gate oxide and its associated defect traps plays a role, though previously reported β-Ga 2 O 3 MOSFETs also show low gate lag [25], [26]. Drain lag is comparable to previous reports, and even at a quiescent drain bias of 25 V, current collapse at V ds,on = 10 V is under 30% (Fig.…”

Progress in Gallium Oxide Field-Effect Transistors for High-Power and RF Applications

“…A modification of the MODFET, named the heterostructure FET (HFET), uses a heavily doped AlGO spacer as opposed to a delta-doping layer with a UID spacer (Figure 15c). E-beam lithography scaled LSG down to 55 nm, reducing the parasitic resistance, reporting near-record fT and fmax values of 30 GHz and 37 GHz, respectively, and minimal RF degradation at temperatures up to 250 °C [96,97]. s −1 at room temperature of an AlGO/GO MODFET using delta doping.…”

“…(c) Cross-section of a heterostructure FET. Reproduced from [96], with the permission of AIP Publishing.…”

Monte‐Carlo‐based simulation study of ion‐implantation in gallium oxide devices

“…A detailed comparative analysis of various losses and damages using dpa calculations during ion implantation for isolation in gallium oxide by Mg and N ions at 50 KeV energy is presented. Furthermore, based on experimental data, generally, the devices (especially FETs) are fabricated with an average epilayer thickness of 200–300 nm 22–24 . So ion dose energy calculation for implant isolation using N and Mg ions for the estimated range of 300 nm depth in the target gallium oxide is also calculated.…”

“…Furthermore, based on experimental data, generally, the devices (especially FETs) are fabricated with an average epilayer thickness of 200-300 nm. [22][23][24] So ion dose energy calculation for implant isolation using N and Mg ions for the estimated range of 300 nm depth in the target gallium oxide is also calculated. This paper also describes various energy losses to ionization, phonons creation, vacancy formation, displacement, damages and replacement collision during implantation process in the target material.…”