Temperature effect on RF/analog and linearity parameters in DMG FinFET

This work investigates the suppressed distortion performance metrics of gate all around (GAA) Gallium Nitride (GaN)/Al2O3 Nanowire (NW) n-channel MOSFET (GaNNW/Al2O3 MOSFET) based on quantum numerical simulations at room temperature (300 K). The simulation results show high switching ratio (≈109) with low subthreshold swing (67mV/decade), high QF value (4.1mS-decade/mV) of GaNNW/Al2O3-MOSFET in comparison to GaNNW/SiO2 and SiNW MOSFET for Vds=0.4V due to the lower permittivity of GaN and more effective mass of the electron. Furthermore, linearity and distortion performance is also examined by numerically calculating transconductance and its higher derivatives (gm2 and gm3); voltage and current intercept point (VIP2, VIP3 and IIP3); 1-dB compression point; Harmonics distortions (HD2 and HD3) and IMD3. All these parameters show high linearity and low distortion at zero crossover point (where gm3=0) in GaNNW/Al2O3 MOSFET. Thus, GaNNW MOSFET can be considered as a promising candidate for low power high-performance applications. In addition, effect of ambient temperature (250K-450K) on the performance of GaNNW/Al2O3 is studied and discussed in terms of the above mentioned metrics. It is very well exhibited that SS, Ion, Vth, and QF improved when the temperature is lowered which makes it suitable for low-temperature environments. But, linearity degrades as the temperature lowers down.

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“…A similar kind of trend is also shown in [28]. Other parameters such as IIP3 and 1-dB Compression Point (CP) are also examined and from Fig.…”

Section: Impact Of Temperaturesupporting

confidence: 67%

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation 

Gupta¹,

Jain

Kumar

2021

Preprint

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“…The turn-on resistance R ON decreases with temperature, and is reduced from 104.6 k (293 K) to 93.7 k (523 K). The trend of V TH and I DS can attributed to an increase in the available free carrier concentration, which escapes from the local state as the temperature increases [30], [31]. The switch current ratio I ON /I OFF decreases from 6.04×10 6 (293 K) to 1.44×10 5 (523 K), as shown in Fig.…”

Section: A Temperature Characteristics Of A-igzo Tftsmentioning

confidence: 81%

High Performance Amorphous IGZO Thin-Film Transistor Based on Alumina Ceramic

et al. 2019

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Ceramic materials are high-temperature resistant materials with promising prospects. In some applications, semiconductor devices need to be integrated with a ceramic substrate. Herein, we report on the stable operation of an Al 2 O 3 ceramic-based amorphous-Indium gallium zinc oxide (a-IGZO) thinfilm transistor (TFT) at room temperature up to 523 K. Scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to characterize the a-IGZO film. A mixed solution was printed on the surface of an insulating layer of alumina. After the combustion reaction, the metal electrode was printed on the surface of a-IGZO to obtain a TFT. The I ON /I OFF ratio was 6.04 × 10 6 at 293 K, and it was maintained at 1.44 × 10 5 at 523 K. It was demonstrated that the parameters of a-IGZO TFTs such as the subthreshold swing (SS), g m and µ sat changed at different temperatures. As such, they can be used as building blocks for integrated circuits that can operate at high temperatures. The fabrication of TFT-based inverters, NAND and NOR gate circuits facilitate the exploration of the possibility of more complex digital circuits that operate at high temperatures, based on hybrid circuit design.INDEX TERMS Al 2 O 3 ceramic, a-IGZO, TFT, high temperature.

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“…The effects of gate dielectrics and VG on intrinsic gain (IG), transconductance frequency product (TFP), gain frequency product (GFP), and gain transconductance frequency product (GTFP) are shown in Figure 11(A–D), respectively. The relations followed for the estimation of IG, TFP, GFP, and GTFP are listed, respectively 45–47 :

italicIG goodbreak= g_{m} / g_{d}

italicTFP goodbreak= ((), g_{m} / I_{D}) goodbreak\times f_{T}

italicGFP goodbreak= ((), g_{m} / g_{d}) goodbreak\times f_{T}

italicGTFP goodbreak= ((), g_{m} / I_{D}) goodbreak\times ((), g_{m} / g_{d}) goodbreak\times f_{T}

Out of the three gate dielectrics, the value of IG peaks for HfO 2 , whereas Si 3 N 4 offers moderate IG (Figure 11(A)) compared to SiO 2 . Also, it is noticed that for low V G values, IG exhibits very low values for all the dielectrics.…”

Section: Resultsmentioning

confidence: 99%

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

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This article reports the DC and analog/radio frequency (RF) response of a newly invented device called vertical super‐thin body (VSTB) FET towards high‐k (Si3N4/HfO2) and low‐k (SiO2) gate dielectrics in conjunction with the scaling effect through a well‐calibrated Sentaurus TCAD tool. At channel length (LG) of 20 nm, compared to SiO2, Si3N4 improves various DC parameters such as off‐state leakage current (Ioff), on‐current (Ion), on‐to‐off current ratio (Ion/Ioff ratio), subthreshold swing (SS), and drain‐induced‐barrier‐lowering (DIBL) by 77.15%, 26.2%, one order of magnitude, 15.78%, and 36.2%, respectively. On the other hand, a higher improvement is seen in all these DC parameters for the HfO2 gate dielectric (Ioff, Ion, Ion/Ioff ratio, SS, DIBL improves respectively by 91.8%, 41.57%, two orders of magnitude, 28.28%, and 62.71%). The underlying physics behind such excellent improvement is explained by the device off‐state energy band diagram, electrostatic potential, and channel electron density profile for each dielectric. Further, for all the gate dielectrics considered, the device characteristics were studied for a wide range of LG from 10 to 50 nm to reveal the scaling impact on the device performance. Irrespective of the gate dielectric material, the device exhibits excellent performance at LG = 10 nm, which in turn indicates to the brilliant scalability of this new device. Besides, although Si3N4 and HfO2 increase gate capacitance (Cgg)/gate‐drain capacitance (Cgd), due to the extremely low values of Cgg/Cgd, enhanced unit gain cut‐off frequency, and gain‐bandwidth‐product is achieved. In addition, the increased transconductance (gm) of the device applying Si3N4/HfO2 gate dielectric leads to a higher peak value of TGF, intrinsic gain, TFP, GFP, and GTFP. This study intends to expand the fundamental knowledge about such a new device as a VSTB FET and hence, aims to be utilized in the future research of this novel device.

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Temperature effect on RF/analog and linearity parameters in DMG FinFET

Cited by 77 publications

References 31 publications

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation

High Performance Amorphous IGZO Thin-Film Transistor Based on Alumina Ceramic

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

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Temperature effect on RF/analog and linearity parameters in DMG FinFET

Cited by 77 publications

References 31 publications

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation&nbsp;

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation&nbsp;

High Performance Amorphous IGZO Thin-Film Transistor Based on Alumina Ceramic

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

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Product

Resources

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Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation

Suppressed Distortion Performance Metrics of 20nm GAA-GaN/Al2O3 Nanowire MOSFET: Based on Quantum Numerical Simulation