Temperature rise effects on static characteristics of complementary FETs with Si and Ge nanosheets

Abstract

We simulate the static behavior of Ge-p/Si-n nanosheet complementary FETs (CFETs), where p-type FETs having Ge nanosheet channels are stacked on top of n-type FETs having Si nanosheet channels, and investigate its relation to temperature while comparing it with that of Si-p/Si-n nanosheet CFETs, whose p-type FETs have Si nanosheet channels. It is found that temperature rise has similar effects on the static characteristics of the two CFETs operating as inverters, although the variations in threshold voltage and noise margin with rising temperature are slightly smaller in the Ge-p/Si-n CFET inverter than in the Si-p/Si-n CFET inverter. These temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.

Effects of Electron Quantum Confinement on Velocity Overshoot in Si Nanosheet Gate-All-Around FETs

“…Moreover, v sat was set to 1.07 × 10 7 cm/s and b to 1.109. Other settings of the DD model have been described in [26]; however, band-to-band tunneling was ignored in this study.…”