Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

Tanougast, Camel; Berviller, Yves; Brunet, Philippe; Weber, S.; Rabah, Hassan

doi:10.1016/s0141-9331(02)00102-3

Cited by 21 publications

(11 citation statements)

References 18 publications

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“…The CDFG of the AES algorithm are initially partitioned in five temporal partitions by the temporal partitioning approach [8]. Next, we calculate all M.S.R values between all successive partitions.…”

Section: Application and Implementation Resultsmentioning

confidence: 99%

“…Next, a temporal partitioning is founded according to the specified constraints and the target applications (constraints of power consumption, logical area, frequency, execution time, etc.) [8,11]. The first step allows us to obtain a set of nature partitions as defined in equation 1.…”

Section: Optimised Temporal Partitioning Based On Inter-partition Synmentioning

confidence: 99%

“…The temporal partitioning divides the target application into a number of specification segments that are destined to be executed one by one in the target reconfigurable hardware device [1]. This allows minimizing the logical area which needs to implement the application while increasing the silicon effectiveness [8]. This technique avoids using oversized resources, but the overall execution time cost is raised during the dynamically reconfigurable (DR) implementation.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A framework of architectural synthesis for dynamically reconfigurable FPGAs

Liu

Tanougast

Weber

2008

2008 IEEE International SOC Conference

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Reconfiguration latency is an important factor which impacts the system performance in the reconfigurable computing design. In this paper, a framework is proposed that presents a novel approach for an optimal implementation of algorithms on FPGA based reconfigurable system. The method optimizes the temporal partitioning by performing a similar-rate-computing-based architectural synthesis. It gives the possibility to merge the related partitions during the implementation of a target architecture by the architectural synthesis based on reusing of the common task. Our approach proposes a final solution based on the computation of the mutual similar rate (M.S.R.) for a RTR implementation with a synthesis option. The proposed approach attempts to reduce the number of the temporal partitions for minimizing the overall execution time. An example is presented to illustrate this novel approach. With the architectural synthesis, the number of partition was decreased. The results demonstrate that are capable and efficient for an optimized implementation in the reconfigurable design.

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Section: Application and Implementation Resultsmentioning

confidence: 99%

Section: Optimised Temporal Partitioning Based On Inter-partition Synmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A framework of architectural synthesis for dynamically reconfigurable FPGAs

Liu

Tanougast

Weber

2008

2008 IEEE International SOC Conference

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“…We can also compare our versatile implementation approach, which is based on the reuse of operators by adding control at different time, to the proposed method based on the temporal partitioning that permits to minimize the array size of a FPGA by using the dynamic reconfiguration feature [30]. All these approaches assume the existence of a resources constraint and the goal of the two approaches is the minimization of hardware resources.…”

Section: Word-length N 8 Bits 12 Bits 16 Bitsmentioning

confidence: 99%

Versatile digital architecture for mobile terminal

Benhaoues

Toumi

Tanougast

et al. 2015

Microprocessors and Microsystems

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“…SPARCS [12] is an integrated partitioning and synthesis framework, which has a temporal partitioning tool to temporally divide and schedule the DFGs on a reconfigurable system. Tanougust et al [15] attempted to find the minimum area while meeting timing constraints during temporal partitioning. In [14], Spillane and Owen focused on finding a sequence of conditions for an optimized scheduling of configurations to achieve the desired trade-offs among reconfiguration time, operation speed and area.…”

Section: Introductionmentioning

confidence: 99%

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit

Mehdipour

Noori

Zamani

et al. 2006

Embedded and Ubiquitous Computing

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Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an RFU. In this paper, our proposed RFU architecture for an adaptive dynamic extensible processor is described. Then, an integrated framework for temporal partitioning and mapping is presented to partition and map the CIs on RFU. In this framework, two mapping aware temporal partitioning algorithms are used to generate CIs. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. Using this framework brings about more speedup for the extensible processor.

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Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

Cited by 21 publications

References 18 publications

A framework of architectural synthesis for dynamically reconfigurable FPGAs

A framework of architectural synthesis for dynamically reconfigurable FPGAs

Versatile digital architecture for mobile terminal

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit

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