Tera-scale computing and interconnect challenges

Abstract

Future CPU directions are increasingly emphasizing parallel compute platforms which are critically dependent upon upon greater core to core communication as well as generally stressing the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon memory bandwidth and latency but must be moderated with power and cost considerations. 3D stacking of CPU's and memory (i.e. a last level cache) is a potential solution that provides the necessary bandwidth within a reasonable power envelope.

Future Directions for Through Silicon Vias

“…Future processors could conceivably consist of (c) 10s to 100s of interconnected Intel Architecture cores with accelerators featuring a local and shared cache model (2). While the transition has relaxed inter-core latency issues and our early motivation for logic to logic to logic stacking it has had a huge impact on memory bandwidth requirements.…”

“…As shown in figure 2 Intel microprocessor design has evolved from (a) deeply pipelined machines optimized for speed and featuring out of order execution towards (b) multi-core machines in which the number and design of cores is optimized to balance single and multi-threaded performance and improved performance per watt. Future processors could conceivably consist of (c) 10s to 100s of interconnected Intel Architecture cores with accelerators featuring a local and shared cache model (2). While the transition has relaxed inter-core latency issues and our early motivation for logic to logic to logic stacking it has had a huge impact on memory bandwidth requirements.…”

Domain-specific processor with 3D integration for medical image processing

“…In the context of GPPs, interface between the L2 cache and main memory is architected using 3D interconnect technology, and performance is compared to a 2D design for memoryintensive applications [6][7][8][9][10]. In the context of FPGAs, a number of recent studies have shown that 3D FPGAs have better performance than existing 2D designs [11][12][13].…”