Domain-specific processor with 3D integration for medical image processing

Cong, Jason; Guruaj, Karthik; Huang, Muhuan; Li, Sen; Xiao, Bingjun; Zou, Yi

doi:10.1109/asap.2011.6043279

Cited by 10 publications

(4 citation statements)

References 20 publications

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“…We evaluate our framework using two core image processing algorithms for 3D MRI, denoise and segmentation. These algorithms are taken from the CPU implementation of the CDSC medical imaging pipeline [1,16,17]. We also evaluate 2 benchmarks from the PolyBench/C test suite, representative of compute-bound and memory-bound numerical kernels.…”

Section: Methodsmentioning

confidence: 99%

Polyhedral-based data reuse optimization for configurable computing

Pouchet

Zhang

Sadayappan

et al. 2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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144

108

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Many applications, such as medical imaging, generate intensive data traffic between the FPGA and off-chip memory. Significant improvements in the execution time can be achieved with effective utilization of on-chip (scratchpad) memories, associated with careful software-based data reuse and communication scheduling techniques.We present a fully automated C-to-FPGA framework to address this problem. Our framework effectively implements data reuse through aggressive loop transformation-based program restructuring. In addition, our proposed framework automatically implements critical optimizations for performance such as task-level parallelization, loop pipelining, and data prefetching. We leverage the power and expressiveness of the polyhedral compilation model to develop a multi-objective optimization system for off-chip communications management. Our technique can satisfy hardware resource constraints (scratchpad size) while aggressively exploiting data reuse. Our approach can also be used to reduce the on-chip buffer size subject to bandwidth constraint. We also implement a fast design space exploration technique for effective optimization of program performance using the Xilinx high-level synthesis tool.

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Section: Methodsmentioning

confidence: 99%

Polyhedral-based data reuse optimization for configurable computing

Pouchet

Zhang

Sadayappan

et al. 2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

Self Cite

144

108

View full text Add to dashboard Cite

show abstract

“…1 Since functions in one block work serially, they can share one memory block without conflicts. That is, the function with the largest memory area determines A mem i,j .…”

Section: ) Function Parametersmentioning

confidence: 99%

“…Domain-specific FPGA accelerators are gaining popularity in heterogeneous multiprocessor systems-on-chip (MPSoCs) [1], [2]. Such accelerators have the potential to provide orders of magnitude improvements in both energy consumption and execution time.…”

Section: Introductionmentioning

confidence: 99%

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications

Liu

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Developing FPGA solutions for streaming applications written in C (or its variants) can benefit greatly from automatic C-to-RTL (C2RTL) synthesis. Yet, the complexity and stringent throughput/cost constraints of such applications are rather challenging for existing C2RTL synthesis tools. This paper considers automatic partition and block-level parallelization to address these challenges. An MILP-based approach is introduced for finding an optimal partition of a given program into blocks while allowing block-level parallelization. In order to handle extremely large problem instances, a heuristic algorithm is also discussed. Experimental results based on seven well known multimedia applications demonstrate the effectiveness of both solutions.

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“…Our proposed system model is a 3D integration of a Field-Programmable Gate Array (FPGA) atop a standard chip multiprocessor (CMP), with Through-Silicon Vias (TSVs) as the communication medium between the two layers ( Figure 1) -a more detailed description of the architecture can be found in [4]. Through 3D integration using TSVs, our design provides efficient and direct CMP-FPGA communication.…”

Section: Introductionmentioning

confidence: 99%

Accelerating vision and navigation applications on a customizable platform

Cong

Grigorian

Reinman

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computationally demanding solutions, it is challenging to achieve high performance without sacrificing the fidelity of results or otherwise consuming excessive amounts of energy. Our goal then is to accelerate the applications in this domain to meet real-time performance constraints while simultaneously reducing energy consumption and avoiding degradation in the quality of results. To achieve this domain-specific acceleration, we model a customizable hardware platform based on the 3D integration of a Field-Programmable Gate Array (FPGA) atop a standard chip multiprocessor (CMP) with Through-Silicon Vias (TSVs) used for communication between the two layers. Furthermore, partial automation of accelerator creation using C-to-RTL tools allows for analysis of a wide range of candidates. In this work, we mathematically characterize viable accelerator candidates, describe ideal application code for acceleration, and outline a dynamic-programming-based methodology for selecting an optimal set of candidates. Our results yield an overall speedup and energy reduction of 9.56X along with a 94X EDP reduction for the domain. Finally, we investigate the effects of various interconnect models on our performance improvements. Overall, our proposed system is shown to be highly efficient in both accelerating performance and saving energy for compute-intensive applications in this domain.

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Domain-specific processor with 3D integration for medical image processing

Cited by 10 publications

References 20 publications

Polyhedral-based data reuse optimization for configurable computing

Polyhedral-based data reuse optimization for configurable computing

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications

Accelerating vision and navigation applications on a customizable platform

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