Test and Design-for-Test of Mixed-Signal Integrated Circuits

Abstract

Although most electronic circuits are almost entirely digital, many include at least a small part that is essentially analog. This is due to the need to interface with the real physical world, that is analog in nature. As demanding market segments require ever more complex mixed-signal solutions, high quality tests become essential to meet circuit design specifications in terms of reliability, time-to-market, costs, etc. In order to lower costs associated to traditional specification-driven tests and, additionally, achieve acceptable fault coverages for analog and mixed-signal circuits, it is reasonable to expect that no other solution than a move towards defect-oriented design-for-test methods will be applicable in the near future. Therefore, testing tends to be dominated by embedded mechanisms to allow for accessibility to internal test points, to achieve on-chip test generation, on-chip test response evaluation, or even to make it possible the detection of errors concurrently to the circuit application. Within this context, an overview of existing test methods is given in this chapter, focusing on design-for-testability, built-in self-test and self-checking techniques suitable for the detection of realistic defects in analog and mixedsignal integrated circuits.Analog and mixed-signal test, fault modelling, fault simulation, test generation, defect-oriented test, design-for-test, design-for-testability, built-in self-test, self-checking circuits. Abstract:Keywords:

Design of a soft-error robust microprocessor

“…Such test can be also performed by simulation as a further verification step to find design errors before an IC fabrication. Other post-fabrication testing approaches are redesigning circuit parts to improve the accessibility to hard-to-test elements as a design-for-testability (LUBASZEWSKI; HUERTAS, 2004). Another approach of design-for-testability such as Built-in Self-Tests (BISTs), tester equipments to apply test vectors are not required due to the on-chip test generation and evaluation.…”

“…Fault simulation is also widely used for evaluation of the test by checking the fault coverage or the percentage of faults detected by a set of input stimuli HUERTAS, 2004). It can be used to measure qualitatively the effectiveness of tests such as the on-line detectors or self-checkers.…”

Experimental Verification of a Ultra-Low Voltage Charge Pump

“…The designer of an integrated circuit must keep the testability of the circuit in mind. This means the tester must have the ability to monitor signal in the important nodes of the circuit (observability) and the ability to insert an external signal into these nodes (controllability) [6].…”

Bulletin of the Polish Academy of Sciences: Technical Sciences

“…Next, low level is kept during the two cycles and four set bits result with 4 system clocks pulse, etc. Besides, as can be noticed in Table 6, many of the testing The six performance parameters (24) of the considered CUT may be self-validated periodically by means of BIST methodology [33][34][35] and for the proposed method this test is completely specified by integer and real numbered above coefficients whose implementation takes less than 2 kB of FLASH memory. Besides, the evolutionarily found digital streams of testing pulses are dedicated to the specific performance parameters and quite easy for generation.…”