Test and Evaluation

doi:10.1002/9781119516699.ch17

Systems Engineering Principles and Practice 2020

DOI: 10.1002/9781119516699.ch17

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Test and Evaluation

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2021

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Study and Analysis of Enclosed Gate FET’s

Vandana

Kumar

Shilla

et al. 2021

IOP Conf. Ser.: Mater. Sci. Eng.

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The characteristic and parametric dimensioning of Enclosed Layout (ELT) MOSFET with various geometric sizes and shapes has been taken into consideration for the study of irradiations and leakage at room temperature, which has been confirmed on several technological platforms. Using the most advanced technologies, parametric changes with minimum W/L ratios, layout area and input capacitance to reduce leakage current can improve the performance. The technique of hardening of the MOSFETs in contrary to total-dose radiation effects in space environment built in enclosure to the enclosed transistor for the elimination of edges, responsible of conventional NMOS transistors leakage path creation. High yielding, high level of integration, radiation immune, high speed, low costing and high volume production are the profit advantages of the enclosed layout.

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Study and Analysis of Enclosed Gate FET’s

Vandana

Kumar

Shilla

et al. 2021

IOP Conf. Ser.: Mater. Sci. Eng.

View full text Add to dashboard Cite

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

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Test and Evaluation

Cited by 1 publication

References 5 publications

Study and Analysis of Enclosed Gate FET’s

Study and Analysis of Enclosed Gate FET’s

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