Abstract:This paper presents a test chip and infrastructure IP (I-IP) solutions to accelerate process development of interconnect on new advanced technology and to improve the back-end-of-line (BEOL) yield on products. The test chip and the I-IP use the same architecture which is described in using a bottom-up approach with emphasis on its scalability. Using this test chip, the specifications of process back-end critical parameters can be quickly and easily analyzed. Using the dedicated infrastructure IP, the defect de… Show more
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