No abstract

No abstract

No abstract

This paper presents a test chip and infrastructure IP (I-IP) solutions to accelerate process development of interconnect on new advanced technology and to improve the back-end-of-line (BEOL) yield on products. The test chip and the I-IP use the same architecture which is described in using a bottom-up approach with emphasis on its scalability. Using this test chip, the specifications of process back-end critical parameters can be quickly and easily analyzed. Using the dedicated infrastructure IP, the defect density tracking as well as the test and diagnosis of process back-end critical parameters can be rapidly and simply performed. To reach this goal, the test flow and its related signature extraction are given. Moreover, each extracted signature is merged in a database which will be used to diagnose defected back-end parameters in the I-IP. Thus, the use of the test chip and the I-IP will allow us to improve the manufacturing process from the beginning of a new technology development and integration to the end of ramp-up production and product manufacturing.

No abstract