Test circuits for fast and reliable assessment of CDM robustness of I/O stages

In this paper, it is demonstrated that low frequency noise measurements are an efficient tool for the detection of latent defects induced by CDM stress in a complex circuit such as a DC-DC converter. This technique is able to detect the presence of a defect whereas classical electrical testing techniques such as Iddq or functionality test fail. In addition, a correlation between the noise signature and the nature of the defect is established. In particular, the presence of trapped charges in the oxides is clearly identified.

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“…To this aim, we used a minimum size MOS transistor (W = 0.8 lm, L = 1.6 lm) as gate monitor (Fig. 6) [8].…”

Section: Discussionmentioning

confidence: 99%

Identification of the physical signatures of CDM induced latent defects into a DC–DC converter using low frequency noise measurements

Gao

Guitard

Salamero

et al. 2007

Microelectronics Reliability

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“…During a CDM test, the accumulated charge on the component will be discharged via the stressed pin (here Vdd pad), causing a remarkable voltage drop along its path by the bus resistance and the clamp voltage of the power clamp [15]. The voltage drop correlates with the distance of the I/O pad and its logic block to the next power clamp.…”

Section: Failure Analysis and Interpretationmentioning

confidence: 99%

CDM tests on interface test chips for the verification of ESD protection concepts

Brodbeck

Esmark

Stadler

2009

Microelectronics Reliability

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“…Consequently, the substrate has a significant influence on the overall circuit behavior. Stadler et al [12] demonstrated that considering the substrate resistance is essential for CDM circuit simulation, especially when packages are used, in which the high capacitance to the ICs backside substrate is contacted. Since the discharge current through the substrate is highly affected by three-dimensional effects, the 3D nature of the substrate has to be considered for the substrate model.…”

Section: Substrate Modelingmentioning

confidence: 99%

“…The p-diffused resistor is embedded in a n-epi well with a n + -buried layer below, which is connected to the cathode of the ESD protection element. Stadler et al [12] performed CDM circuit simulation, using lumped resistor elements for substrate and buried layer resistance. Substrate/n + -buried layer diode and capacitance were also considered.…”

Section: Simulation Of Cdm Failure Mechanismmentioning

confidence: 99%