Due to the reaction time of the devices, the rise time of an ESD pulse has a strong effect on the efficiency of a protection network. (vf-)TLP clearly causes different failure modes depending on the rise time. This knowledge is needed to design protections that can handle fast ESD transients..This paper addresses the phenomena that may happen 1. IntrOClllCtlOn in the first few nanoseconds of an ESD pulse. This is Designing adequate ESD protection networks for done via experiments witii (vf-)TLP witii different rise meeting HBM, CDM or system level ESD times and TCAD simulations Usmg test structures it specifications requires good characterization of the ^^^ ''^ .^^own that, depending on the rise time, devices. Due to several recent advances the different failure modes may be obtained, characterization possibilities have been extended.TT A Vi While the effect of current densities and pulse width A^* ApproaCIl has received much attention, [l]-[3], less is known j^^ measurements described in this paper were done about the impact of the rise time of the discharge on ^-^^^ ^^^-^^^^ TLP and vf-TLP systems. Unless stated the device behaviour. It has been shown [4] that otherwise all data is taken on-wafer. TLP applying a faster rise time with TLP leads to a lower characteristics are given until the last good point, with apparent trigger voltage. It has also been shown that ^ 2X leakage current increase criterion. The test the rise times in so-called real HBM can be much structures are either stand-alone ESD protection faster than those allowed by the standards [5]. As elements or ESD protections with efficiency monitors discussed in [6] and [7], fast ESD transients lead to [^3]^ [^4] ^^ illustrated in Figure 1. In all cases the different failure modes than pure HBM and MM monitor is a thin gate oxide device, stress. Much of these effects are related to the difference between robustness and efficiency of a protection (network). Robustness means the ability of an ESD protection to sink the discharge current. Efficiency is the ability to do so at a sufficiently low voltage. A well-known contributor to the efficiency is the dynamic resistance (Ron) of the protection. We will show that the reaction time of the protection is another large contributor. Rise time effects have been analysed by device simulations in [8] and were shown ^.^^^^ ^. ^,\,,^^ti. of BSD protection with efficiency monitor to cause voltage overshoots. It is possible to extract (left). A backside SEM photograph ofthe monitor is shown on the device turn-on behaviour from (vf-)TLP right, measurements [9]-[ll]. Often a major part of measured overshoots are actually artefacts and Measurements show that the DC breakdown voltage disappear after careful de-embedding [12]. Although of the gate oxide is 7 V. For 100 ns pulses the that is definitely correct we will show that in several breakdown voltage increases to 8.5 V and for 10 ns situations the rise time effects may actually damage pulses to 9 V. vulnerable circuitry, as was stipulated in [11].^^^ ^j^^ ^j^^ ^^...

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