Test cost and test power conflicts: EDA perspective

Hirech, M.

doi:10.1109/vts.2010.5469599

Cited by 2 publications

(3 citation statements)

References 5 publications

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“…For a given test data set containing m vectors with n bits each, the weighted transition for each test vector is given by (1), and the total weighted transition during test is given by (2), Weighted Transitions for Scan-In vector j…”

Section: Weighted Transition-based Reordering Columnwise Bit Fillingmentioning

confidence: 99%

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Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

2011

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Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like "don't care bit filling" and "reordering" which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed "Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)" is a modification to earlier proposed "Hamming Distance based Reordering-Columnwise Bit Filling and Difference vector." This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow.

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Section: Weighted Transition-based Reordering Columnwise Bit Fillingmentioning

confidence: 99%

“…The testing cost and testing power are the two well-known issues of current generation IC testing [1].…”

Section: Introductionmentioning

confidence: 99%

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

2011

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“…The test cost is directly related to test data volume and hence the test data transfer time [1]. The test cost is directly related to test data volume and hence the test data transfer time [1].…”

Section: Introductionmentioning

confidence: 99%

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

Sruthi

2012

Progress in VLSI Design and Test

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Today's electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS'89 benchmark circuits.

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Test cost and test power conflicts: EDA perspective

Cited by 2 publications

References 5 publications

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power

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