Test generation for current testing of bridging faults in CMOS VLSI circuits

Lee, T.; Hajj, I.N.

doi:10.1109/mwscas.1995.504443

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A Inter-gate Bridging Fault1

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“…To reduce the number of fault sets that will be considered by a time-consuming SAT-based ATPG, we run random simulation first as is the same method already proposed [12] [13].…”

Section: A Inter-gate Bridging Faultmentioning

confidence: 99%

SAT-based ATPG testing of inter- and intra-gate bridging faults

Nakura

Tatemura

Fey

et al. 2009

2009 European Conference on Circuit Theory and Design

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This paper presents an ATPG framework for IDDQ testing of both intra-and inter-gate bridging faults. The framework integrates random simulation and a deterministic stage using Boolean SATisfiability (SAT) as the underlying engine. This decides whether a fault is testable or untestable. In this way, we conduct an exact search for test patterns for IDDQ testing of both intra-and inter-gate bridging fault detection.

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“…To reduce the number of fault sets that will be considered by a time-consuming SAT-based ATPG, we run random simulation first as is the same method already proposed [12] [13].…”

Section: A Inter-gate Bridging Faultmentioning

confidence: 99%