Test generation for sequential circuits

Ma, H.-K.T.; Devadas, Srinivas; Newton, A.R.; Sangiovanni-Vincentelli, A.

doi:10.1109/43.7807

Cited by 173 publications

(26 citation statements)

References 11 publications

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“…A gate-level fault simulator is used to verify if other faults are detected by the same sequence. As do other TPG algorithms [8], we assume a reset state exists. Since STT descriptions were not available for benchmar circuits, they were extracted.…”

Section: Methodsmentioning

confidence: 99%

Functional test generation for FSMs by fault extraction

Vinnakota

Andrews

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG algorithms utilize a functional description of a circuit. Multilevel TPG algorithms attempt to realize the advantages of both approaches through fault translation. In such systems, gate-level faults are translated to functional faults and TPG is performed at the functional level. We develop and present new techniques for fast ecient fault translation from the logic to the functional level. These techniques are implemented in a m ulti-level sequential circuit test generation system. Performance results for benchmark circuits are presented.

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Section: Methodsmentioning

confidence: 99%

Functional test generation for FSMs by fault extraction

Vinnakota

Andrews

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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“…However, the problem still lacks a breakthrough. At the gate-level, a number of deterministic test generation tools, both academic [1,2] and commercial, have been implemented. None of these methods can efficiently handle sequential designs of even a couple of thousands of gates.…”

Section: Introductionmentioning

confidence: 99%

High-Level Decision Diagram based Fault Models for Targeting FSMs

Raik

Ubar

Viilukas

2006

9th EUROMICRO Conference on Digital System Design (DSD'06)

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Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern generation. Those methods have proven efficient. However, all of them target modules inside the datapath of the circuit. In this paper, we show by experiments that the fault coverage achieved by full datapath tests is often lower than what can be achieved if faults in the control part FSM were additionally considered. We also propose a new type of fault model for targeting faults in FSMs embedded to RTL descriptions. In addition, we present an alternative for traditional assignment decision diagrams, which provides for a more general representation of RTL circuits. We show that our model, called high-level decision diagrams, allows efficient high-level test path activation. According to experiments the proposed approach outperforms state-ofthe-art test pattern generation tools.

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“…Algorithms using the RTP approach, such as the Back [8] algorithm using the Split [9] circuit model of Gentest [10], map the required previous state of a current time frame to the next time frame for justification. Stallion [11] and Steed [12] use precomputed state transition diagrams and cubes, respectively. Hitec [13] combines PODEM [14] with the dominators and the mandatory assignments of Fan [15], TOPS [16] and Socrates [17].…”

Section: Introductionmentioning

confidence: 99%

Sequential circuit test generation using dynamic justification equivalence

Chen

Bushnell

1996

J Electron Test

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Automatic test pattern generation (ATPG) for sequential circuits involves making decisions in the search decision spaces bounded by a sequential circuit. The flip-flops in the sequential circuit determine the circuit state search decision space. The inputs of the circuit define the combinational search decision space. Much work on sequential circuit ATPG acceleration focused on how to make ATPG search decisions. We propose a new technique to improve sequential circuit ATPG efficiency by focusing on not repeating previous searches. This new method is orthogonal to existing deterministic sequential circuit ATPG algorithms.A common search operation in sequential circuit ATPG is justification, which is to find an input assignment to justify a desired output assignment of a component. We have observed that implications in a circuit resulting from prior justification decisions form an unique justification decomposition. Since the connectivity of a circuit does not change during ATPG, test generation for different target faults may share identical justification decision sequences represented by identical decision spaces. Because justification decomposition represents the collective effects of prior justification decisions, it is used to identify previously-explored justification decisions. Preliminary results on the ISCAS 1989 circuits show that our test generator (SEST) using justification decompositions, on average, runs 2.4 and 4.5 times faster than Gentest and Hitec, respectively. We describe the details of justification equivalence and its application in ATPG accompanied with step-by-step examples.

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Test generation for sequential circuits

Cited by 173 publications

References 11 publications

Functional test generation for FSMs by fault extraction

Functional test generation for FSMs by fault extraction

High-Level Decision Diagram based Fault Models for Targeting FSMs

Sequential circuit test generation using dynamic justification equivalence

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