Abstract-In this paper, we address the problem of the state assignment for synchronous finite state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations. Optimal state assignment aims at a minimum area implementation. All previous work in automatic FSM state assignment has been directed at programmable logic array (PLA) i.e., two-level logic implementations. In practice, most large FSM's are not synthesized as a single PLA for speed and area reasons-multilevel logic implementations are generally used for smaller delay and area. In this paper, we present state assignment algorithms that heuristically maximize the number of common cubes in the encoded network so as to minimize the number of literals in the resulting combinational logic network after multilevel logic optimization. We present results over a wide range of benchmarks which prove the efficacy of our techniques. Literal counts averaging 20-40 percent less than other state assignment programs have been obtained.

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It is well known that optimal logic synthesis can ensure fully testable combinational logic designs. In this paper we show that optimal sequential logic synthesis can produce irredundant, fully testable finite state machines. Test generation algorithms can be used to remove all the redundancies in sequential machines resulting in a fully testable design. However, this method may require exorbitant amounts of CPU time. The optimal synthesis procedure presented in this paper represents a more efficient approach to achieve 100% testability.Synthesizing a sequential circuit from a State Transition Graph description involves the steps of state minimization, state assignment and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignment and logic optimization. In this paper we show that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. Unlike previous synthesis approaches to ensuring fully testable machines, there is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. (/ j) Given a State Transition Graph specification, a logic-level automaton that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements is synthesized. This procedure represents an alternative to a Scan Design methodology without the usual area and performance penalty associated with the latter method. * 90 01 16 147 1iaosystns Massachusetts Cambddge Roam 39421 Technology Inasilu Massachusetts Telephone Labonaodes of Technology 02139 -(617) 2530292 I Accesiot) For NTiS CFA&I 4 DTIC TAB 0 J istlf if ut,,., By O~stfibujtio I Av ciltbihty Codes --", Dst I 14-7/. ,tt dAbstract optimal sequential logic synthesis can produce fallv testable nonscan finite state machines. Test generation algorithms can be used It is well known that optimal logic synthesis can ensure fully to remove all the redundancies in sequential machines resulting in testable combinational logic designs. In this paper. we show that fuily testable designs. However. in general. this method requires optimal sequential logic synthesis can produce irreduudant, fully exorbitant amounts of CPU time. The optimal synthesis procetestable finite state machines. Test generation algorithms can be dure presented in this paper represents a more efficient approach used to remove all the redundancies in sequential machines resultto achieve 100% testability. ing in a filly testable design. However. this method may require Synthesizing a sequential circuit from a State Transition Graph exorbitant amounts of CPU time. The optimal synthesis procedescription involves the steps of state minimization. state assigiidure presented in this paper represents a more efficient approach ment and logic optimization. Previous approaches (...

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