On the over-specification problem in sequential ATPG algorithms

Cheng, Kwang-Ting; Ma, H.-K.T.

doi:10.1109/43.256935

Cited by 17 publications

(9 citation statements)

References 12 publications

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“…However, there is no guarantee that these assignments will be minimal. Cheng et al, [7] describes a procedure for finding minimal assignments in ATPG search. The algorithm requires search during the decision procedure and can be expensive, but is complete.…”

Section: Structural Algorithm Terminationmentioning

confidence: 99%

“…This was targeted for image computation and is quite different from REDUCEASSIGNMENTS, since a) we perform DFS-like search in the sequential space and b) we perform quantification of subsets of state-variables in a time-frame. The approach by Cheng et al, [7], performs search for minimal assignments, which can be quite expensive, while ours is a linear-time algorithm.…”

Section: Related Workmentioning

confidence: 99%

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SATORI-a fast sequential SAT engine for circuits

Iyer

Parthasarathy

Cheng

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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We describe the design and implementation of SATORI -a fast sequential justification engine based on state-of-the-art SAT and ATPG techniques. We present several novel techniques that propel SATORI to a demonstrable 10x improvement over a commercial engine. Traditional sequential justification based on ATPG or, on a bounded model of the sequential circuit using SAT, has diverging strengths and weaknesses. In this paper, we contrast these techniques and describe how their strengths are combined in SATORI. We use conflict-based learning in each timeframe and illegal state learning across time-frames. This enables both combinational and sequential back-jumping. We experimentally analyze the main features of SATORI by comparing SATORI's performance against a state-of-the-art SAT solver -ZCHAFF [13] using a bounded model, and a commercial sequential ATPG engine performing justification. Additional results are presented for SATORI versus the commercial ATPG engine and VIS [16] on ISCAS '89 and ITC'99 benchmark circuits for an application to assertion checking.

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Section: Structural Algorithm Terminationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

SATORI-a fast sequential SAT engine for circuits

Iyer

Parthasarathy

Cheng

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…2(b) when we know b = 0 would cause a conflict, we immediately set b = 1 by default. This practice is illegal for sequential circuits [40] since it would prune unexplored decision spaces in either the fault-free or the faulty circuit from the search process, causing the justification to be incomplete.…”

Section: Justification Decompositionmentioning

confidence: 99%

Sequential circuit test generation using dynamic justification equivalence

Chen

Bushnell

1996

J Electron Test

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Automatic test pattern generation (ATPG) for sequential circuits involves making decisions in the search decision spaces bounded by a sequential circuit. The flip-flops in the sequential circuit determine the circuit state search decision space. The inputs of the circuit define the combinational search decision space. Much work on sequential circuit ATPG acceleration focused on how to make ATPG search decisions. We propose a new technique to improve sequential circuit ATPG efficiency by focusing on not repeating previous searches. This new method is orthogonal to existing deterministic sequential circuit ATPG algorithms.A common search operation in sequential circuit ATPG is justification, which is to find an input assignment to justify a desired output assignment of a component. We have observed that implications in a circuit resulting from prior justification decisions form an unique justification decomposition. Since the connectivity of a circuit does not change during ATPG, test generation for different target faults may share identical justification decision sequences represented by identical decision spaces. Because justification decomposition represents the collective effects of prior justification decisions, it is used to identify previously-explored justification decisions. Preliminary results on the ISCAS 1989 circuits show that our test generator (SEST) using justification decompositions, on average, runs 2.4 and 4.5 times faster than Gentest and Hitec, respectively. We describe the details of justification equivalence and its application in ATPG accompanied with step-by-step examples.

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“…Hence, these lines have three decision options (0, 1 , and Z / U ) (see Figure 2 ) . The value U on PPIs is necessary in order to avoid overspecified states (i.e., states containing assigned values, which do not contribute to the detection of the faultunder-test) and to assure complete search in TPG for sequential circuits (STPG) [4]. Justification of an o mspecified state can result in longer test sequences, or even worse, in incorrectly declaring a fault untesta ble.…”

Section: Figure 1 A) a Bus-conflict B) An Incorrectly Assumed Bus-cmentioning

confidence: 99%

Complete search in test generation for industrial circuits with improved bus-conflict detection

Linden

Konijnenburg²,

Goor³

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

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Test P a t t e r n Generation (TPG) forsequential and/or %state circuits involves t w o important aspects which often are handled incorrectly: Bus conflict detection and completeness of search an TPG. T h e correct handling of both aspects strongly depends o n the signal model used by TPG. W e propose a novel, set-based, signal model using the power-set (i.e., the set of all possible subsets) of the basic values { 0 , 1 , Z } . TPG using this signal model guarantees complete search, provides exact bus-conflict detection, and is 'more e f i c i e n t t h a n TPG using the traditional signal models for 3-state and sequential circuits. Experimental results demonstrate this by higher fault eficiencies combined with a large reduction of backtracking and computing t i m e f o r seqvential ISCAS'89 and industrial circuits.

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On the over-specification problem in sequential ATPG algorithms

Cited by 17 publications

References 12 publications

SATORI-a fast sequential SAT engine for circuits

SATORI-a fast sequential SAT engine for circuits

Sequential circuit test generation using dynamic justification equivalence

Complete search in test generation for industrial circuits with improved bus-conflict detection

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