A synthesis and optimization procedure for fully and easily testable sequential machines

Abstract. We investigate the gate-delay-fault testability properties of multilevel, multiplexor-based logic circuits. Based on this investigation, we describe a procedure for synthesizing gate-delayfault testable multilevel circuits. The procedure involves the construction of a multilevel circuit from a general, unordered Binary Decision Diagram (BDD) by replacing vertices of the BDD with multiplexors. The procedure relies on the following result derived in this article: If the multilevel circuit constructed from the BDD is initially fully single stuck-at fault testable, or made fully single stuck-at fault testable by redundancy removal, then it is completely robustly gate-delay-fault testable. Once the initial gate-delay-fault testable circuit has been obtained, constrained algebraic factorization is used to improve the area and performance characteristics without compromising testability. Unlike previous techniques for synthesizing robustly gate-delay-fault testable circuits, this procedure can be used to synthesize fully testable circuits directly from nonflattenable, logic-level implementations.

show abstract

“…Synthesis methods are also being applied to sequential circuits under stuck-at [4] and delay faults models (e.g., [5]). …”

Section: Introductionmentioning

confidence: 99%

Gate-delay-fault testability properties of multiplexor-based networks

Ashar¹,

Devadas

Keutzer

1993

Form Method Syst Des

View full text Add to dashboard Cite

show abstract

“…In some problems, a constraint is satisfied if the corresponding function fi is respected in every column of the constraint, like code compatibility constraints [2] or output constraints [3]. There are also cases where the fi need to be satisfied in a specific number of encoding columns [5]. That is why the domain of the satisfaction functions gi are all possible encodings of length k. Given this mapping, the state assignment problem can be reduced to the general BCE problem, and we need to look for an optimum encoding h of the state set Q, such that k is the minimum possible and c(h) is maximum.…”

Section: Problemmentioning

confidence: 99%

“…To satisfy one such constraint one encoding column suffices. Distance-2 constraints were proposed in [5] to guarantee fully stuck-at testable state assignment for FSMs. One such constraint is satisfied only if a Hamming distance of 2 is obtained between the codes of the symbols involved in it.…”

Section: Constraint Classesmentioning

confidence: 99%

Boolean Constrained Encoding: A New Formulation And A Case Study

Calazans¹

IEEE/ACM International Conference on Computer-Aided Design

View full text Add to dashboard Cite

“…The following constraints are imposed on the logic synthesis process in order to result in a fault-secure implementation. During state encoding, all valid controller states are constrained to have the same parity [14]. The outputs are also constrained to be encoded with the same parity with the help of an extra output.…”

Section: Moves In the Iterative Improvement Proceduresmentioning

confidence: 99%

“…The controller finite-state machine (FSM) is made faultsecure by constraining the state encoding procedure to assign codes having the same parity to all the states and, in addition, constraining the primary outputs and next state outputs of the controller to be implemented by disjoint cones of logic [14]. The parity of the primary outputs of the controller is also generated as a controller output.…”

Section: Introductionmentioning

confidence: 99%

Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis

Lakshminarayana

Raghunathan

Jha

Proceedings of Annual Symposium on Fault Tolerant Computing

View full text Add to dashboard Cite

AbstractÐThis paper addresses the problem of synthesizing fault-secure controller/data path circuits from behavioral specifications. These circuits are guaranteed to either produce the correct output, or to flag an error. We use an iterative improvement-based behavioral synthesis framework that performs functional unit selection, clock selection, scheduling, and resource sharing with the aim of minimizing the area of the synthesized circuit, while allowing multicycling, chaining, and functional unit pipelining. We present a dynamic comparison selection algorithm that can be used during behavioral synthesis to determine which intermediate results in the computation need to be secured in order to enable maximal resource sharing. Previous work on synthesizing fault-secure data paths has focused on ensuring that aliasing (a condition when the circuit produces an incorrect output and does not flag an error) cannot occur in any part of the design. We demonstrate that such an approach can lead to unnecessarily large overheads. In order to alleviate the overheads incurred for fault security, our behavioral synthesis framework uses ALiasing Probability analysiS (ALPS) in order to identify resource sharing configurations that reduce area while introducing a very low probability of aliasing (of the order of IH ÀIH for a bit-width of 32) in the resultant data path. Experimental results performed for several behavioral descriptions demonstrate that our techniques synthesize more compact circuits than techniques available in the literature, e.g., double moIdular redundancy or zeroaliasing techniques.

show abstract

A synthesis and optimization procedure for fully and easily testable sequential machines

Cited by 79 publications

References 12 publications

Gate-delay-fault testability properties of multiplexor-based networks

Gate-delay-fault testability properties of multiplexor-based networks

Boolean Constrained Encoding: A New Formulation And A Case Study

Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis

Contact Info

Product

Resources

About