Test-model based hierarchical DFT synthesis

Abstract

With increasing design sizes and adoption of System on a Chip (SoC) IntroductionRecent advances in manufacturing and methodology allow for larger and more complex IC designs. In today's environment, circuit sizes typically exceed million gates introducing further complexity to the design flow in terms of timing, placement and routing. This, coupled with the increasing relevance of the design-reuse paradigm suggests that capacity and performance will soon become major concerns with most DFT tools. In the past, DFT flows advocated a top-down approach to synthesize, optimize and insert test logic on flattened designs. Today, Design re-use and System on a Chip (SoC) methodologies [1] are driving the shift towards hierarchical flows, where pre-assembled blocks are integrated with control logic to form a complete system. These flows recommend a bottom-up approach to perform DFT synthesis on large hierarchical designs. Designers develop blocks concurrently, synthesizing them and implementing DFT at the front end of the design process. This enables predictability and facilitates optimization to minimize the impact of test logic on the design. Once all the blocks are complete and DFT ready, final assembly integrates them and addresses DFT at the chip-level. If each of these blocks is over a million gates large, then reading in the entire design and performing DFT insertion at the chip-level becomes impractical. In addition we also have to account for glue logic between these blocks which might be significant.The concept of test modeling presents a solution to this problem. Test modeling refers to the abstraction of DFT structures embedded in a design, in the form of a test model. In other words, a test model encapsulates all DFT information needed by a system integrator. The proposed HDS flow uses a test model instead of a netlist representation of the sub-modules during chip-level integration. Thus, we realize a significant improvement in terms of both capacity and performance since the size of the abstract model is typically only a small fraction of the original netlist.The use of test models instead of complete netlists presents us with a number of challenges, in terms of reusing existing proven technology. In this context we address Design Rule Checking (DRC), DFT architecting and optimization.DRC can be applied stand-alone, to validate test design rules or as a pre/post-processor to DFT synthesis, to extract information for the purpose of DFT modeling such as sequential cells that violate test design rules and scan chain information. Our implementation of DRC in a traditional DFT synthesis flow is simulation based and therefore relies on the availability of a gate-level netlist. To leverage this technology we present a technique by which we extract representative netlists from test models.DFT Closure, that is to rapidly and predictably meet all DFT requirements from RTL to GDSII [2], is a mandate for most designs. This needs to be achieved at every stage in the design process, particularly at the chip-le...

Fully X-tolerant combinational scan compression

“…In such cases, a hierarchical approach (Figure 13) can be adopted by partitioning the design into modules, inserting compression logic at the module-level and then integrating the blocks at the design-level ( Figure 14). The DFT logic in a sub-module can be abstracted in the form of a test model which can be used instead of the full netlist representation of the module during integration [22]. In this case, the modulelevel DFT signals are automatically connected to designlevel ports and information about module-level compression logic is automatically promoted to the design-level protocol file.…”