Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost

Zhou, Bin; Liyi, Xiao; Ye, Yizheng; Wu, Xinchun; Cao, Bei

doi:10.1166/jolpe.2012.1167

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2014

2021

Publication Types

Select...

Article1

Other1

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

Priya

Sarada

2021

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

This work presents a new approach for built-in test pattern generation (BIST) based on the variable rate clock-driven linear feedback shift register (LFSR) and twisted-ring counters (TRCs). The proposed technique operates on different operating clocks for generating deterministic test pattern sequence for the circuit under test (CUT). The test vectors generated by LFSR are transformed and reproduced with TRC results. The TRC design constitutes of only flip-flops, which be used as a potential alternative to improved seed storage and complex multi polynomial configurations in LFSR. Moreover, the control logic is simplified with synchronized multi-rate clock generation and can be easily extended for any test cubes among multiple CUTs. The randomness characteristics of LFSR are retained with improved memory efficiency and considerable complexity reduction. Experimental results validate the proposed test pattern generator (TPG) over existing well-known LFSRs models, and its randomness is proved with ISCAS benchmark circuits.

show abstract

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

Priya

Sarada

2021

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

A Low Power Test-per-Clock BIST Scheme through Selectively Activating Multi Two-Bit TRCs

Zhou

2014

2014 Fourth International Conference on Instrumentation and Measurement, Computer, Communication and Control

View full text Add to dashboard Cite

Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost

Cited by 2 publications

References 0 publications

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

A Low Power Test-per-Clock BIST Scheme through Selectively Activating Multi Two-Bit TRCs

Contact Info

Product

Resources

About