Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SoCs

Abstract

Many SOCs contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SOCs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. However, the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bitwidth used to access it. We present a scalable test planning technique that exploits port scalability of testers to reduce SOC test time.We compare the proposed heuristic optimization method to two baseline methods based on prior work that use a single scan data rate for all the embedded cores.

A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise

“…There have been many approaches to solve this problem, including on-chip data converters to convert mixed-signal circuits into virtually digital ones [13,14,15,12,10], the use of on-chip circuitry that eases the requirements on the analog test signals [18,4], analog signal sources and analyzers on the tester board [3], and specialized on-chip test circuitry to target the desired parameters of the mixed-signal circuit [11,17,16,7,1]. Examples of these techniques will be discussed in more detail in the next section.…”

Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE

“…With the debut of a new class of multi-port ATE, there is a pressing need for test planning methods to exploit new concurrent test capabilities of these ATEs. Some recent work [8,9] on TAM optimization has introduced the use of dual-speed or multiple-speed ATEs that drives the channels at two different speeds or within a data rate range. However, the restriction on the number of available ATE ports and partitioning-based port assignment prevent these approaches from fully utilization of the flexible per-pin architecture that supports tremendous capability to dynamically reconfigure ports.…”