Test Set Development for Cache Memory in Modern Microprocessors

Al-Ars, Zaid; Hamdioui, Said; Gaydadjiev, Georgi; Vassiliadis, S.

doi:10.1109/tvlsi.2008.2000257

Cited by 15 publications

(4 citation statements)

References 33 publications

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“…There are established methodologies for targeted testing of cache memory at very low level as found in [24]. More standard techniques are outlined in the work published in [25].…”

Section: Related Workmentioning

confidence: 99%

A Search Based Approach for Stress-Testing Integrated Circuits

Eljuse

Walkinshaw

2016

Search Based Software Engineering

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Abstract. In order to reduce software complexity and be power efficient, hardware platforms are increasingly incorporating functionality that was traditionally administered at a software-level (such as cache management). This functionality is often complex, incorporating multiple processors along with a multitude of design parameters. Such devices can only be reliably tested at a 'system' level, which presents various testing challenges; behaviour is often non-deterministic (from a software perspective), and finding suitable test sets to 'stress' the system adequately is often an inefficient, manual activity that yields fixed test sets that can rarely be reused. In this paper we investigate this problem with respect to ARM's Cache Coherency Interconnect (CCI) Unit. We present an automated search-based testing approach that combines a parameterised test-generation framework with the hill-climbing heuristic to find test sets that maximally 'stress' the CCI by producing much larger numbers of data stall cycles than the corresponding manual test sets.

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“…There are established methodologies for targeted testing of cache memory at very low level as found in [24]. More standard techniques are outlined in the work published in [25].…”

Section: Related Workmentioning

confidence: 99%

A Search Based Approach for Stress-Testing Integrated Circuits

Eljuse

Walkinshaw

2016

Search Based Software Engineering

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“…The value of C g is considered to be a typical 500fF [10], while Cg Cb values are modified for each simulation in the range 1 ≤ C g /C b ≤ 20 [4], with used C b values as 500fF, 100fF, 50fF, 30fF and 25fF.…”

Section: A Simulated Open Defectsmentioning

confidence: 99%

“…From a testing perspective, it is possible to use BL coupling to introduce extra stress on specific faults, thereby making them easier to detect by a given test [4]. Furthermore, it is essential to understand how a specific initialization of a neighborhood of cells affects the sensing of a given faulty cell, in order to write such worst-case values in the neighboring cells (worst stress condition) during testing.…”

Section: Introductionmentioning

confidence: 99%

Bit line coupling memory tests for single-cell fails in SRAMs

Irobi

Al-Ars

Hamdioui

2010

2010 28th VLSI Test Symposium (VTS)

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Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper evaluates the impact of bit line coupling in SRAMs on cell faulty behavior and identifies necessary conditions to induce worst-case coupling effects.We present a test that guarantees detecting all singlecell static faults in the presence of capacitive coupling and worst-case neighborhood data for any possible open defect.

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“…Also, the concept of dynamic faults has been established in SRAMs [2], [4]. However, no work has been done on evaluating the impact of parasitic node capacitance on the faulty behavior of SRAMs [7], [1], which can cause dynamic faults. In addition, no detection mechanism nor memory tests have been developed that account for this faulty behavior in SRAMs.…”

Section: Introductionmentioning

confidence: 99%

Parasitic memory effect in CMOS SRAMs

Irobi

Al-Ars

Renovell

2010

2010 5th International Design and Test Workshop

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The presence of parasitic node capacitance on a defective resistive node can induce dynamic changes in the electrical behavior of the circuit in SRAM devices, which may be referred to as the parasitic memory effect. This effect can cause dynamic faults in SRAMs. This paper presents an analysis of the parasitic memory effect in SRAMs on the defective resistive node. The paper demonstrates that the faulty behavior in SRAMs is exacerbated in the presence of parasitic node capacitance, something that reduces the fault coverage of current memory tests, and increases the defect-per-million rates.

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Test Set Development for Cache Memory in Modern Microprocessors

Cited by 15 publications

References 33 publications

A Search Based Approach for Stress-Testing Integrated Circuits

A Search Based Approach for Stress-Testing Integrated Circuits

Bit line coupling memory tests for single-cell fails in SRAMs

Parasitic memory effect in CMOS SRAMs

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