Test Strategies for Low-Power Devices

Abstract

Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the target application, there are stringent guidelines on the number of defective parts per million shipped devices. At the same time, since such devices are cost-sensitive, test cost is a major consideration. Since system-level power-management techniques are employed in these devices, test generation must be power-management-aware to avoid stressing the power distribution infrastructure in the test mode. Structural test techniques such as scan test, with or without compression, can result in excessive heat dissipation during testing and damage the package. False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss. This paper considers different aspects of testing low-power devices and some new techniques to address these problems.

Detectability analysis for resistive open faults with dynamic supply voltage scaling awareness

“…Testing multiple supply voltage aware designs and dynamic supply voltage and frequency scaling aware de signs specifically for physical defects involves several chal lenges, mainly due to the various design techniques and ar chitectures employed as well as the inconsistent detectabil ity pattern of faults as a function of supply voltage [19], [17], [10]. Additionally, applying the conventional testing methods at all operating condition settings is a straight forward approach, but would dramatically increase testing time and cost especially for large devices.…”

Power-aware test generation with guaranteed launch safety for at-speed scan testing

“…• Problem-1 (Unfocused Effect): Previous techniques only reduce the total LSA for the whole circuit in an unfocused manner. However, the real cause for timing failures (i.e., excessive LSA in neighboring areas around long sensitized paths) often remains [6,8]. In addition, unfocused LSA reduction constrains too many logic values in a test vector, causing test quality degradation and test data inflation.…”

“…This means that function-mode-oriented wafer / package level heat management and power supply network (PSN) design are getting relatively weaker with respect to potentially excessive test power [5]. As a result, heat-related test safety (i.e., over-heat may damage circuits) and power-supply-noise-related test safety (i.e., power supply noise may invalidate test responses) have become serious problems in at-speed scan testing [5,6].…”

A scan shifting method based on clock gating of multiple groups for low power scan testing

“…As a result, the incremental temperature and current density require expensive test packages to tolerate excessive heat during test [6]. On the other hand, the peak power which means the highest power in a cycle leads to erroneous data transfer and fails test results [7].…”

“…To improve efficiency of the scan-based testing, there are two major solutions to reduce excessive test power in the research works: automatic test pattern generation (ATPG)based and DFT-based [7]. The ATPG-based solution analyzes and/or controls the test patterns for reduction of test power [9].…”