Test Strategies for Reconfigurable Scan Networks

Kochte, Michael A.; Baranowski, Rafał; Schaal, Marcel; Wunderlich, Hans-Joachim

doi:10.1109/ats.2016.35

Cited by 10 publications

(4 citation statements)

References 20 publications

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“…Nodes n 1 , n 2 and n 3 are located at the top level scan segment, while nodes n 31 , n 32 and n 33 are accessible through n 3 (located in its input segment(s)). Nodes n 11 (1, 1) and n 13 (1, 1) provide access only to empty segments and segments that include either TDRs or control bits (registers), which is obviously not the case with the node n 12 (1,2). This node provides access to the segment at the second level of hierarchy with one node n 121 (2, 2) in it.…”

Section: Algorithmmentioning

confidence: 99%

“…4c). (1,3) n 122 (2,3) n 2 (0,0) n 3 (0,2) n 31 (1,1) n 32 (1,2) n 33 (1,1) n 1 (0,3) n 12 ( IV. EXPERIMENTS We developed a prototypical tool, able to build an internal simplified RSN model by reading the ICL description of the network.…”

Section: Algorithmmentioning

confidence: 99%

“…Since both production test and in-field monitoring processes majorly depend on such embedded instruments and other features, it is of utmost importance to ensure their correct operation. Therefore, many approaches, both formal and functional, have been proposed in the literature to perform test [2]- [7], diagnosis [8] and verification [9]- [11] of IEEE 1687 networks. However, the correct operation of IJTAG-compliant infrastructure is a product of many aspects and components including the actual hardware on the chip, the respective standard descriptions, such as ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) files as well as the software used to import the descriptions and control the hardware.…”

Section: Introductionmentioning

confidence: 99%

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Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Damljanovic

Jutman²,

Squillero

et al. 2019

2019 IEEE European Test Symposium (ETS)

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The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standardthe IEEE 1687. Such a standard resorts to a reconfigurable scan network to provide efficient and flexible access to instruments and to handle complex structures. As it has to deliver reliable service, many approaches, both formal and simulation-based, have been proposed in the literature to perform test, diagnosis and verification of such networks. This paper focuses on the problem of post-silicon validation of a network, a problem that has not been adequately addressed, yet. We analyze the mismatches between the specification and its silicon implementation, and we propose a methodology to detect a subset of them by applying functional patterns and observing the length of the active scan path. Experimental results on ITC2016 benchmarks demonstrate that the proposed approach is broadly applicable, and able to generate very effective sequences. We also classify mismatches that cannot be targeted relying exclusively on the active scan path length information.

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Section: Algorithmmentioning

confidence: 99%

Section: Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Damljanovic

Jutman²,

Squillero

et al. 2019

2019 IEEE European Test Symposium (ETS)

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“…In [Jut16] a methodology for fault tolerant transmission over IJTAG networks has been proposed for enhancing the reliability of transmission. In addition, self-test techniques of the network are possible using approaches such as proposed in [Koc16] or [Can15]. Other reliability techniques for reliable network transmission, such as data protection by appending CRC or parity bits, can be employed for ensuring a reliable transmission over an IJTAG network.…”

Section: Reliabilitymentioning

confidence: 99%

Test standards reuse for structured and cost-efficient dependability management of system-on-chips

Ibrahim¹

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A Complete Design-for-Test Scheme for Reconfigurable Scan Networks

2022

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Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

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Test Strategies for Reconfigurable Scan Networks

Cited by 10 publications

References 20 publications

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Test standards reuse for structured and cost-efficient dependability management of system-on-chips

A Complete Design-for-Test Scheme for Reconfigurable Scan Networks

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