Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hashempour, H.; Dohmen, Jos J.; Tasic, B.; Kruseman, B.; Hora, C.; Beurden, M. van; Xing, Yizi

doi:10.1109/date.2011.5763065

Cited by 21 publications

(13 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, we present the algorithm for deriving the set C 1 in (2) that defines the parametric fault model F in (3) and the set C 2 ( ) in (5) that defines the set of marginally functional circuits instances Y( ) in (6). The algorithm targets specifically the derivation of C 1 and as a by-product it also derives C 2 ( ).…”

Section: Algorithmmentioning

confidence: 99%

See 1 more Smart Citation

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Stratigopoulos

Sunter²

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

International audienceThe accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to directly measure datasheet specifications. To reduce the involved costs it is required to eliminate specification tests or use instead lower-cost alternative tests. However, this is too risky if the resultant fault coverage and yield coverage metrics of the new test approach are not estimated accurately. This paper proposes a methodology to efficiently derive a set of most probable failing and marginally functional circuit instances. Based on this set, we can readily define and estimate fault coverage and yield coverage metrics. Our methodology reduces the required number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the methodology is applied to a radio frequency low-noise amplifier

show abstract

Section: Algorithmmentioning

confidence: 99%

“…This approach has led to defect-oriented test techniques [6]- [8] which can be applied for wafer-level testing to detect dies with gross defects or for final testing of robust designs that are highly unlikely to fail due to process variations.…”

Section: Introductionmentioning

confidence: 99%

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Stratigopoulos

Sunter²

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…This approach has led to defect-oriented test techniques [2], [3] which can be applied for wafer-level testing to detect dies with gross defects or for final testing of robust designs that are highly unlikely to fail due to process variations.…”

Section: Introductionmentioning

confidence: 99%

Efficient Monte Carlo-based analog parametric fault modelling

Stratigopoulos

Sunter²

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to measure datasheet specifications. The lack of a comprehensive fault model that is computationally efficient makes the elimination of any tests or the use of lower-cost alternative tests too risky or too time-consuming. Monte Carlo simulations offer a general way to model parametric variations, but inherently focus on normal instead of defective performance. This paper defines a new, general fault model comprising a set of marginally failing circuit instances to evaluate parametric fault coverage of test suites in a way that reduces the number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the technique is applied to six parameters of an RF low-noise amplifier (LNA).

show abstract

“…An Inductive Fault Analysis (IFA) like approach utilizes the layout details of a design [16]. This methodology is adopted in [17] to extract the shorts/bridges for an industrial mixed signal chip, where the layout details are passed to a parasitic capacitor extractor and the capacitance values are used to calculate the probability of short between two nets. These nets can be either, two metal tracks, two polysilicon layers or a metal and a polysilicon layer.…”

Section: Introductionmentioning

confidence: 99%

A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices

Rai

Hashempour

Xing

et al. 2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

View full text Add to dashboard Cite

This paper presents a defect extraction methodology for dislocation anomalies in analogue-mixed signal (AMS) Integrated Circuits (ICs). Dislocation defects can cross the PN junction of a transistor/diode and contribute to leakage related failures. The extraction of dislocation defects from layout information is very difficult. We propose a methodology that accepts a schematic (netlist) of the AMS design and generates a list of dislocation defects by identifying the hierarchical net names of each defect. The methodology parses the schematic (netlist) and locates dislocation defects according to pre-determined rules. The cross section of different devices from the design manual of a process technology are studied and the possible dislocation spots related to PN junctions are listed in a rule file. This methodology is applied to five AMS IC products and a considerable amount of simulation time can be saved by truncating the defect list to the extracted dislocation susceptible spots.

show abstract

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Cited by 21 publications

References 25 publications

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Efficient Monte Carlo-based analog parametric fault modelling

A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices

Contact Info

Product

Resources

About