Test vector decompression via cyclical scan chains and its application to testing core-based designs

Jas, A.; Touba, N.A.

doi:10.1109/test.1998.743186

Cited by 224 publications

(137 citation statements)

References 18 publications

Supporting

Mentioning

137

Contrasting

Order By: Relevance

“…They described a BIST scheme for non-scan circuits based on statistical coding using comma codes (very similar to Huffman codes) and run-length coding. A scheme for compression/decompression of test data using cyclical scan chains is described in [16]. It uses careful ordering of the test set and formation of cyclical scan chains to achieve compression with run-length codes.…”

Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

View full text Add to dashboard Cite

Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

show abstract

Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

View full text Add to dashboard Cite

show abstract

“…Most use special decompression hardware on the chip [2,3,9,10,12,16]. In this paper, we focus on software-based test data compression techniques that are applicable to deterministic test vectors since the test vectors for a core in a SoC are usually precomputed by the vendor.…”

Section: Introductionmentioning

confidence: 99%

Matrix-based software test data decompression for systems-on-a-chip

Balakrishnan

Touba

2004

Journal of Systems Architecture

View full text Add to dashboard Cite

This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the processorÕs on-chip memory. The processor executes a program which decompresses the data and applies it to the scan chains of each core-under-test. The matrix-based operations that are used to decompress the test vectors can be performed very efficiently by the embedded processor thereby allowing the decompression program to be very fast and provide high throughput of the test data to minimize test time. Experimental results demonstrate that the proposed approach provides greater compression than previous methods.

show abstract

“…A promising approach for reducing test data volume for SOCs is based on data compression techniques [2,3]. In this approach, the precomputed test set Test data can be more efficiently compressed by exploiting the fact that the number of bits changing between successive patterns in a test sequence is generally very small.…”

Section: Introductionmentioning

confidence: 99%

“…In this approach, the precomputed test set Test data can be more efficiently compressed by exploiting the fact that the number of bits changing between successive patterns in a test sequence is generally very small. This observation was used in [3], where a "difference vector" sequence ference vectors and based on cyclical scan registers (CSRs) is sketched in Figure 1. A drawback of the compression method described in [3] is that it relies on variable-to-fixedlength codes, which are less efficient than more general variable-to-variable-length codes [5,6].…”

Section: Introductionmentioning

confidence: 99%

“…This observation was used in [3], where a "difference vector" sequence ference vectors and based on cyclical scan registers (CSRs) is sketched in Figure 1. A drawback of the compression method described in [3] is that it relies on variable-to-fixedlength codes, which are less efficient than more general variable-to-variable-length codes [5,6]. Furthermore, it is inefficient for cores with internal scan chains that are used to capture test responses; in these circuits, separate CSRs increase hardware overhead.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Chandra¹,

Chakrabarty²

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001

View full text Add to dashboard Cite

show abstract

Test vector decompression via cyclical scan chains and its application to testing core-based designs

Cited by 224 publications

References 18 publications

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Matrix-based software test data decompression for systems-on-a-chip

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Contact Info

Product

Resources

About