Matrix-based software test data decompression for systems-on-a-chip

Abstract

This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the processorÕs on-chip memory. The processor executes a program which decompresses the data and applies it to the scan chains of each core-under-test. The matrix-based operations that are used to decompress the test vectors can be performed very efficiently by the embedded processor thereby allowing the decompression program to be very fast and provide high throughput of the test data to minimize test time. Experimental results demonstrate that the proposed approach provides greater compression than previous methods.

Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs

“…Balakrishnan et al (Balakrishnan and Touba 2004) present a novel matrix-based software data compression scheme. The same authors also proposed decompression for deterministic vectors using linear operations (Balakrishnan and Touba 2005).…”

Multiple modular very long instruction word processors based on field programmable gate arrays

“…Today SoCs have become omnipresent because of the advances in design technology that make it possible to build complete systems containing different types of components on the same chip. [1][2][3][4] There will likely be a market explosion with very tough competition, and factors such as cost, performance, and time-to-market will be very important for the success of a product.…”