Testability Analysis of Circuits using Data-Dependent Power Management

Abstract

Power dissipation has recently emerged as one the most critical design constraints. Data-dependent power management techniques are among the most effective for power reduction. Depending on some input conditions, the clock driving some of the registers in the circuit is inhibited, thus reducing the switching activity in the fanout of those registers.The use of data-dependent power management techniques creates some interesting testability problems. The signals used to inhibit the clock can dramatically reduce the observability of the nodes in the circuit. In this paper, we first describe an approach for the complete testing of power-optimized circuits using these techniques. We then present results that show that using state-of-the-art techniques, ATPG for the power managed circuit is not significantly more difficult than for the original circuit.