Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

Abstract

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the [Formula: see text]-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm2 area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.

Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

“…The V gate is the square root of NOT gate and the V + gate is the Hermitian conjugate of the V gate [3,10]. The V and V + gates have the following properties [5,6]:…”

“…In order to construct a truth table for V and V + gates, the properties of these gates are used, as proposed in Equation ( 2) [3]. This equation shows that when two V gates or two V + gates are in series it is equal to a NOT gate.…”

“…Also, when either two consecutive NOT gate or consecutive controlled V and V + gate is present the quantum cost will be zero [3], as shown in Figure 3. 1.…”

“…The reversible logic circuits are constructed using a distinguished well-defined library of gates. Good reversible logic circuits must be well optimized in terms of quantum cost (QC), constant input (CI), garbage output (GO) and logical calculations (LC) [3]. The reversible logic circuits are established in quantum cellular automata and optical computation.…”

Regular clocking scheme based design of cost-efficient comparator in QCA

“…The concept of QCA clocking is briefly described in details in [12,18,19]. In this regard, QCA has received a numerous attention for the past few years in the logic design specially towards arithmetic logic such as adders [20,21], multiplexer [22][23][24][25], XOR [26][27][28], parity checker [29][30][31], comparators [32][33][34][35][36][37][38][39][40]. Among them, comparators have received a considerable interest as it is having an important role in the development of central processing unit (CPU) and also widely studied.…”