Testing 90 nm microcontroller SRAM PUF quality

Barbareschi, Mario; Battista, Ermanno; Mazzeo, Antonino; Mazzocca, Nicola

doi:10.1109/dtis.2015.7127360

Cited by 23 publications

(7 citation statements)

References 8 publications

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“…Largescale evaluations of RO PUFs on 217 FPGAs [34], [35], and 133 ASICs [36] show that the location of cells within the FPGA affect performance properties. The bit-alias of uninitialized SRAM between 50 [37] and 144 [33] devices reveals a slight double-peaked distribution of the bit-alias scores due to SRAM layout systematics, but seem to miss convergence due to an insufficient sample size.Wilde et al [6] identify a research gap in convergence and deduce that qualified inter-device bit-alias measurements require more than 600 devices to converge with an error below 5%.…”

Section: Empirical Evaluation Of Pufsmentioning

confidence: 99%

PUF for the Commons: Enhancing Embedded Security on the OS Level

Kietzmann¹,

Schmidt²,

Wählisch³

2023

Preprint

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Security is essential for the Internet of Things (IoT). Cryptographic operations for authentication and encryption commonly rely on random input of high entropy and secure, tamper-resistant identities, which are difficult to obtain on constrained embedded devices. In this paper, we design and analyze a generic integration of physically unclonable functions (PUFs) into the IoT operating system RIOT that supports about 250 platforms. Our approach leverages uninitialized SRAM to act as the digital fingerprint for heterogeneous devices. We ground our design on an extensive study of PUF performance in the wild, which involves SRAM measurements on more than 700 IoT nodes that aged naturally in the real-world. We quantify static SRAM bias, as well as the aging effects of devices and incorporate the results in our system. This work closes a previously identified gap of missing statistically significant sample sizes for testing the unpredictability of PUFs. Our experiments on COTS devices of 64 kB SRAM indicate that secure random seeds derived from the SRAM PUF provide 256 Bits-, and device unique keys provide more than 128 Bits of security. In a practical security assessment we show that SRAM PUFs resist moderate attack scenarios, which greatly improves the security of low-end IoT devices.

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Section: Empirical Evaluation Of Pufsmentioning

confidence: 99%

PUF for the Commons: Enhancing Embedded Security on the OS Level

Kietzmann¹,

Schmidt²,

Wählisch³

2023

Preprint

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“…The advantage of this proposed metric lies in its ability to identify the optimal combination of wand r for achieving the most stable outcomes in an SRAM. Furthermore, it offers insights that can be extrapolated to the analysis of all SRAMs of the same kind [19].…”

Section: Neighborhood Pair Analysismentioning

confidence: 99%

Accelerated Aging Effects on SRAM PUF reliability at various Temperature and Voltage conditions

Singh,

Bhatta,

Rahman

et al. 2023

Preprint

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This paper thoroughly investigates the trustworthiness of Static Random-Access Memory (SRAM) Physical Unclonable Functions (PUFs) within hardware security. It presents an overview of SRAM PUFs, their significance in hardware security, and their essential features. The paper explores the realms of evaluation metrics and practical examination of SRAM cell start-up values concerning an 8-bit SRAM dataset. Concurrently, it navigates the encountered challenges. A comprehensive pattern analysis of SRAM cell stability is discussed with accelerated aging. Compared the outputs at multiple trials to authenticate the result. The complex interplay of factors that affect the dependability of SRAM PUFs, encompassing environmental conditions, the accumulation of aging effects, and the complex landscape of process variations, is carefully explained and clarified. The paper concludes by summarizing key findings, emphasizing the importance of reliable hardware security, and suggesting future research directions for enhancing SRAM PUF reliability.

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“…Therefore, the challenge can be used as the address of an SRAM cell, and the initial value of it can be used as the SRAM PUF response. It is also possible to implement SRAM PUFs on micro-controllers [54,55,56], but implementing them on FPGAs is not straightforward (Criterion 4). This makes them an unpopular choice for FPGA-based PUFs for the IoT [7,17,57].…”

Section: Physical Unclonable Function Architecture Selection For Iotmentioning

confidence: 99%

Physical Unclonable Functions in the Internet of Things: State of the Art and Open Challenges

Babaei

Schiele

2019

Sensors

128

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Attacks on Internet of Things (IoT) devices are on the rise. Physical Unclonable Functions (PUFs) are proposed as a robust and lightweight solution to secure IoT devices. The main advantage of a PUF compared to the current classical cryptographic solutions is its compatibility with IoT devices with limited computational resources. In this paper, we investigate the maturity of this technology and the challenges toward PUF utilization in IoT that still need to be addressed.

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Testing 90 nm microcontroller SRAM PUF quality

Cited by 23 publications

References 8 publications

PUF for the Commons: Enhancing Embedded Security on the OS Level

PUF for the Commons: Enhancing Embedded Security on the OS Level

Accelerated Aging Effects on SRAM PUF reliability at various Temperature and Voltage conditions

Physical Unclonable Functions in the Internet of Things: State of the Art and Open Challenges

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