Testing a DSP-Based Mixed-Signal Telecommunicatians Chip

Abstract

Testability enhancements used in the design, development, and production of a 1.6 million transistor mixed-mode telecommunications integrated circuit are described. Integrated test features include a test block which provides an interface to the chip bus during test, scan test circuitry for testing of individual blocks, special circuitry to allow isolation of the digital and arialog portions of ihe chip during test, and an on-chip debugger incorporated in software. In addition to facilitating high volume, low cost testing with high quality fault coverage, the testability enhancements reported in this paper also allowed concurrent development of the digital and analog portions of the chip and resulted in a dramatic decrease in product development time.