Testing embedded cores using partial isolation rings

The fault coverage for bridge defects in the bit-cell matrix of the initial FIFO test has been improved by inclusion of an additional data background and lowvoltage testing. 100% fault coverage is reached for low resistance bridges. The fault coverage for opens has been improved by a new test procedure including waiting periods.98.4% of the hard bridge defects in the asynchronous control slices can be detected with some modifications of the initial test. Nyckelord KeywordsFIFO testing, FIFO, testing, defect-based testing AbstractNXP Semiconductors (formerly Philips Semiconductors) has created a new embedded asynchronous FIFO module. It is a small and fast full-custom design with Design-for-Test (DfT) functionality. The fault detection qualities of a proposed manufacturing test for this FIFO have been analyzed by a defect-based method based on analog simulation. Resistive bridges and opens of different sizes in the bit-cell matrix and in the asynchronous control have been investigated. The fault coverage for bridge defects in the bit-cell matrix of the initial FIFO test has been improved by inclusion of an additional data background and lowvoltage testing. 100% fault coverage is reached for low resistance bridges. The fault coverage for opens has been improved by a new test procedure including waiting periods.98.4% of the hard bridge defects in the asynchronous control slices can be detected with some modifications of the initial test.

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“…Instead of implementing a full test wrapper, we implemented only a partial wrapper [25]. We used wrapper cells like IEEE Std.…”

Section: Modular Test With Partial Test Wrappermentioning

confidence: 99%

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Dubois

Marinissen

Azimane

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Recently a number of approaches have addressed the core wrapper design [3,[13][14][15] and the TAM design [13][14][15][16][17][18][19][20][21] issues. With respect to core wrapper design, the work in [13] proposes a "test collar"…”

Section: Previous Workmentioning

confidence: 99%

Addressing useless test data in core-based system-on-a-chip test

Gonciari

Al-Hashimi

Nicolici³

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Several DFT approaches were introduced to minimize the hardware cost of the serial scan ring around a core, by using existing functional flip-flops, mixing internal and external FFs, or using compaction and expansion [4] [13]. In realistic examples often a combination of serial and parallel access cells are used for a given core, where the data patterns are applied through the serial ring, whereas the clocks and control signals are asserted via parallel access.…”

Section: Serial Scan Accessmentioning

confidence: 99%