A novel design-for-test (DFT) technique is presented for designing a core with a "virtual scan chain" which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a normal scan chain. For the system integrator, testing a core with a virtual scan chain is identical to testing a core with a normal scan chain. The only difference is that the virtual scan chain is much shorter so the size of the scan vectors and output response is smaller resulting in less test data and fewer scan shift cycles. The process of mapping the virtual scan vectors to real scan vectors is handled inside the core and is completely transparent to the system integrator. It is done by using LFSRs to "expand" the shorter virtual test vector into a full test vector. Results indicate that virtual scan chains can be designed which are several times shorter than the real scan chains inside the core.

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Abstract

Abstract

In today's large designs, especially large SOC (system-on-a-chip) designs, vector volume for a single core could dominate the memory resources of the target tester and leave little or no room for other vectors. To this end, delivery of an "optimized or "reduced vector set, without any loss of coverage, is preferred. One commercial means of delivering an optimized vector set is to compress the vectors during vector generation. Another applicable solution is to understand the overlapping faults among various fault models and remove them from the fault lists for certain pattern types. The main problem with these optimization approaches is that compressed vectors create more switching activities, which could potentially cause average power dissipation, instantaneous and peak power during test to be significantly higher than normal operation. Test power is such a big concern in large SOC designs that the power associated with the "reuse" vectors must be understood. This paper presents a case study of a Motorola Version 3 ColdFire@ microprocessor core, with a focus on the various vector optimizations and their ramifications on test power.