Testing embedded sequential cores in parallel using spectrum-based BIST

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

2007

We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on inputs-outputs of the different modules/registers in the circuit, and the vectors are analyzed using Hadamard matrices for Walsh functions and the random noise level at each primary input. This information then helps generate vector sequences. At the gate-level, a fault simulator and an integer linear program (ILP) compact the test sequences. RTL test appraisal also helps reveal the hard-to-test parts of the circuit. An XOR observability tree was used to improve the testability of those parts. We give results for a simple accumulator-based processor named Parwan. The RTL spectral vectors produced higher coverage in shorter CPU times as compared to a gate-level ATPG.

Section: Introductionmentioning

confidence: 99%

Spectral RTL Test Generation for Microprocessors

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

2007

“…More recently, Giani et al [11], [12] have reported spectral techniques for sequential ATPG and built-in self-test. Hsiao et al [6], [7] have published works on spectrum-based self test and core test. Zhang et al [36] refined the method of extracting the spectra from a digital signal using a selfish gene algorithm.…”

Section: Introductionmentioning

confidence: 99%

Transition Delay Fault Testing of Microprocessors by Spectral Method

2007 Thirty-Ninth Southeastern Symposium on System Theory

2007

We introduce a novel spectral method of delay test generation for microprocessors at the register-transfer level (RTL). Vectors are first generated by an available ATPG tool for transition faults on inputs and outputs of the RTL modules of the circuit. These vectors are analyzed using Hadamard matrices to obtain Walsh function components and random noise levels for each primary input. A large number of vector sequences is then generated such that all sequences have the same Walsh spectrum but they differ due to the random noise in them. At the gate-level, a fault simulator and an integer linear program (ILP) compact these vector sequences. The initial RTL vector generation also reveals the hard-to-test parts of the circuit. An XOR observability tree was used to improve the testability of those parts. We give results for an accumulator-based processor named Parwan. The RTL technique produced higher gate-level transition fault coverage in shorter CPU time as compared to a gate-level transition fault ATPG.

“…More recently, Giani et al [9,10] have reported spectral techniques for sequential ATPG and built-in self-test. Hsiao's group at Virginia Tech has published further work on spectrum-based self test and core test [2,3,16]. Khan and Bushnell [17] have designed hardware signature analyzers using spectral components.…”

Section: Introductionmentioning

confidence: 99%

Spectral RTL Test Generation for Gate-Level Stuck-at Faults

2006 15th Asian Test Symposium

2006

We model RTL faults as stuck-at faults on primary inputs, primary outputs, and flip-flops. Tests for these faults are analyzed using Hadamard matrices for Walsh functions and random noise level at each primary input. This information then helps generate vector sequences. At the gate-level, a fault simulator and an integer linear program (ILP) compact the test sequences. We give results for four ITC'99 and four ISCAS'89 benchmark circuits, and an experimental processor. The RTL spectral vectors performed equally well on multiple gate-level implementations. Compared to a gatelevel ATPG, RTL vectors produced similar or higher coverage in shorter CPU times.