Testing Gbps interfaces without a gigahertz tester

Mak, T.M.; Tripp, M.; Meixner, A.

doi:10.1109/mdt.2004.42

Cited by 23 publications

(6 citation statements)

References 6 publications

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“…For external memory, applications for testing these components exist within System-in-Package (SiP) with numerous abilities of debug [5] are being integrated into FPGAs. Another application of board-level BIST is testing high-speed I/O within ASICs to fully characterize AC parameters and debug faults [6]. Versions of this testing solution are being sold and integrated into FPGAs by third party vendors as well.…”

Section: Previous Workmentioning

confidence: 99%

FPGA-based universal embedded digital instrument

Ferry

2013

2013 IEEE International Test Conference (ITC)

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In order to test products, a multi-purpose digital instrument has been developed which can be completely embedded within on-board FPGAs. This instrument incorporates numerous features such as specialized triggering, fault capture, and pattern edge placement. To increase usability, pattern generation and protocol-aware features are included within its small footprint. The applications of the embedded instrument can include design verification, production test, and fault diagnostics in a simple and low resource implementation.

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Section: Previous Workmentioning

confidence: 99%

FPGA-based universal embedded digital instrument

Ferry

2013

2013 IEEE International Test Conference (ITC)

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“…Given that ATE pin electronics for high performance interfaces are the highest cost adder to a test platform, pursuing IO DFT based test methods permits the usage of low cost testers. Following the course laid out in [2], a combination of DFT based test methods, external loopbacks and ATE test methods enable using low speed digital ATEs for HSIO test on our products today. As discussed in [2,3,4] the ATE configurations fall into 2 scenarios: In addition to loopback on High Speed IO, product teams have developed comprehensive structured test solutions for measuring the key parameters required to ensure the performance and quality.…”

Section: Hvm Test Practicesmentioning

confidence: 99%

Improving IO test and system evaluation via data sharing

Meixner

Abdennadher

2012

7th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

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High speed I/O circuits are becoming increasingly critical as technology scales to increase system bandwidth and decrease power dissipation, die area and system cost. Highly integrated SOCs are currently equipped with large numbers of serial links to enable processing of high bandwidth data streams. There are two major challenges to continued scaling of highspeed I/Os: band-limited channels and timing uncertainty that require a good knowledge on customer system usage. In addition the increase push for customer differentiation and OEM's pushing more designs to low cost and less skilled design teams adds to the challenge. Adequate learning data sharing between customers and silicon provider is key in these emerging markets to meet quality and Time to Market targets

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“…In practice, only the minimum and maximum limits on phase and voltage offsets are measured, which intend to guarantee the I/O performance margin in production testing [3][4][5]. We will illustrate that such a test might not detect some chips that fail the BER specification when the random jitter (RJ) accounts for a non-trivial fraction of the total jitter (TJ).…”

Section: Figure 1 Block Diagram Of a Transceivermentioning

confidence: 99%

“…To alleviate these test challenges, several design-fortest (DFT) techniques have been recently proposed [3][4][5][6][7]. The most popular and efficient approach to testing a serial transceiver is based on the loopback principle, which can test most of the transceiver's functionality without relying on very expensive high-speed and high-pin-count ATE [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing

Hong¹,

Cheng²

2007

16th Asian Test Symposium (ATS 2007)

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This paper describes a technique for estimating total jitter that, along with a loopback-based margining test, can be applied to test high speed serial interfaces. We first present the limitations of the existing estimation method, which is based on the dual-Dirac model. The accuracy of the existing method is extremely sensitive to the choice of the fitting region and the ratio of deterministic jitter to random jitter. Then, we propose a high-order polynomial fitting technique and demonstrate its value for a more efficient and accurate total jitter estimation at a very low Bit-Error-Rate level. The estimation accuracy is also analyzed with respect to different numbers of measurement points for fitting. This analysis shows that only a very small number (i.e., 4) of measurement points is needed for achieving accurate estimation.16th IEEE Asian Test Symposium

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Testing Gbps interfaces without a gigahertz tester

Cited by 23 publications

References 6 publications

FPGA-based universal embedded digital instrument

FPGA-based universal embedded digital instrument

Improving IO test and system evaluation via data sharing

An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing

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