Testing micropipelines

Khoche, A.; Brunvand, Erik

doi:10.1109/async.1994.656316

Cited by 22 publications

(9 citation statements)

References 8 publications

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“…The latter ones, i.e., delay faults, are also often the subject of research in testing asynchronous circuits [5]- [9]. Depending on the type of the asynchronous circuit, delay faults can be more or less critical.…”

Section: Fault Modelsmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globallyasynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.

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Section: Fault Modelsmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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“…However, timing faults resulting in bundling constraint violation are not considered. Khoche et al [4] and Petlin et al [5] developed full-scan approaches for testing micro-pipelines. Their methods are able to test not only for stuck-at faults but also for delay faults resulting in bundling constraint violation.…”

Section: Previous Workmentioning

confidence: 99%

“…A number of methods have been proposed in the past for testing asynchronous pipelines [3,4,5,6,7,8]. Most * This work is partially supported by the DARPA CLASS program.…”

Section: Introductionmentioning

confidence: 99%

Test generation for ultra-high-speed asynchronous pipelines

Shi

Makris

Nowick

et al.

IEEE International Conference on Test, 2005.

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We propose a methodology for testing ultra-high-speed asynchronous pipelines, the latest and most promising asynchronous circuit design style. Unlike traditional delayinsensitive asynchronous micro-pipelines, which use slow capture-pass latches, these circuits employ aggressive handshaking protocols and transparent latches between fine-grain pipeline stages, in order to achieve high performance. Their functional robustness, however, relies on certain timing constraints that need to be satisfied. As a result, these circuits are no longer delay-insensitive, which means that stuck-at faults will not always lead to pipeline stalling. In addition, delay faults may result in violation of these timing constraints, thus affecting not only performance, as in delay-insensitive micro-pipelines, but also functional correctness. To address these new challenges, we develop a test method for both stuck-at and timing constraint violation faults in fine-grain ultra-high-speed asynchronous pipelines. The efficiency of the proposed method is demonstrated on MOUSETRAP, a recently developed pipeline for high-speed applications.

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“…Despite the growing number of recent efforts in the specification and design of asynchronous circuits, testing of these circuits has not been explored to any great degree. Very few efforts have been made in this area compared to efforts in synchronoustesting [11,13,14,18,19,20,21,22,23,27].…”

Section: Introductionmentioning

confidence: 97%

ACT: a DFT tool for self-timed circuits

Khoche

Brunvand

Proceedings International Test Conference 1997

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This paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based selftimed circuits testable. The ACT tool is the first oFits kind for testing macro-module based self-timed circuits. ACT modifies designs automatically to incorporate partial scan and provides a complete path from schematic capturie to physical layout. It also has a test generation system to generate vectors for the testable design and to compute fault coverage of the generated tests. The test generatioin system includes a module for doing critical hazard free (.est generation using a new 6-valued algebra. ACT has been h i l t around commercial tools from Viewlogic and Cascade. A Viewlogic schematic is used as the design entry point and Cascade tools are used for technology mapping.

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Testing micropipelines

Cited by 22 publications

References 8 publications

A survey about testing asynchronous circuits

A survey about testing asynchronous circuits

Test generation for ultra-high-speed asynchronous pipelines

ACT: a DFT tool for self-timed circuits

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