Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip

Karimi, Naghmeh; Kong, Zhiqiu; Chakrabarty, Krishnendu; Gupta, Pallav; Patil, S.

doi:10.1109/ats.2011.68

Cited by 11 publications

(3 citation statements)

References 5 publications

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“…However, repeated invocation of the commercial logic simulator leads to extremely long runtimes. Moreover, the tests derived in [9] do not target at-speed transfer of transition of data required between the clock domains, hence their effectiveness for highspeed circuits is questionable.…”

Section: Introductionmentioning

confidence: 98%

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Test generation for clock-domain crossing faults in integrated circuits

Karimi

Chakrabarty

Gupta

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Clock-domain crossing (CDC) faults are a serious concern for high-speed, multi-core integrated circuits. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems that affect data transfer across clockdomain boundaries for fabricated chips. We present a test generation technique that leverages commercial ATPG tools, but introduces additional constraints, to detect CDC faults. We also present HSpice simulation data using a 45 nm technology to quantify the occurrence of CDC faults at clock-domain boundaries. Results are presented for synthesized IWLS05 benchmarks that include multiple clock domains. The results highlight the ineffectiveness of commercial transition-delay fault ATPG and the "coverage gap" resulting from the use of ATPG methods employed in industry today. While the proposed method can detect nearly all CDC faults, TDF ATPG is found to be severely deficient for screening CDC faults.

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Section: Introductionmentioning

confidence: 98%

“…A testpattern selection method for detecting CDC faults was recently proposed in [9]. A commercial ATPG tool and a commercial logic simulator were used to extract, from a pattern repository, a set of test patterns that detect CDC faults.…”

Section: Introductionmentioning

confidence: 99%

Test generation for clock-domain crossing faults in integrated circuits

Karimi

Chakrabarty

Gupta

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…They can be composed of several processor cores attached to hardware accelerators and memories for performance enhancement of parallel computation and multithreading. Every single unit shares common buses and caches, which can be the critical part of the system performance if not properly managed [3].…”

Section: Introductionmentioning

confidence: 99%

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

et al. 2023

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The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device.

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Improved test methodology for multi-clock domain SoC ATPG testing

Ooi

Ang

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip

Cited by 11 publications

References 5 publications

Test generation for clock-domain crossing faults in integrated circuits

Test generation for clock-domain crossing faults in integrated circuits

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

Improved test methodology for multi-clock domain SoC ATPG testing

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