The 100% yield explanation approach in Lucent Technologies Madrid

Recio, Miguel; Merino, Miguel Alonso; Martin, V.; Ayucar, Jose Ángel; Moreno, Julián; Godino, Agustin; Mata, Carlos; Morilla, Carmen Rodríguez; Lorenzo, Alfonso; Fernández, René; Fernández, Almudena; Iñarrea, Jesús; Álvarez, María Arias; Sacedon, Ana; Mateos, Carlos; Therryl, K.; González, Gerardo; Cruceta, Sergio

doi:10.1109/asmc.2000.902554

Cited by 3 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Detecting issues in the early stage of chip manufacturing can save money and improve yield ramp cycle time [1]. Key defect modes are detected inline and resolved before functional testing using various defect inspection methodologies.…”

Section: Introductionmentioning

confidence: 99%

Methodologies for fast yield ramp with limited engineering resources utilizing Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics

Muthumalai

Ling

Ross

et al. 2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

View full text Add to dashboard Cite

Yield ramp is a significant metric in determining the profitability of the semiconductor industry. Defect inspection methodologies play a major role in detecting key defect modes inline before functional testing. A fast, production ready Yield learning methodology is needed to quantify the impact of inline detected and non-detected defects and to provide a way of determining the priority of processes. This information helps the engineering teams to highlight critical yield-limiting defects and facilitate an understanding of failure modes. Current conventional strategies have limitations of inaccuracy and larger cycle time. The methodologies presented in this paper utilize Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics for fast yield ramp in limited engineering resources. These methodologies have demonstrated exceptional cycle time reduction on cutting edge 28nm, 20nm and 14nm test chips including customer products.

show abstract

Section: Introductionmentioning

confidence: 99%

Methodologies for fast yield ramp with limited engineering resources utilizing Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics

Muthumalai

Ling

Ross

et al. 2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

View full text Add to dashboard Cite

show abstract

SmartBit/sup TM/: bitmap to defect correlation software for yield improvement

Merino¹,

Cruceta²,

García³

et al.

2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072)

View full text Add to dashboard Cite

The need of higher yields on the wafermanufacturing environment is pushing the yield analysts to develop new techniques and tools for yield improvement. With this scope, we present SmartBitTM, a software tool that provides detailed information about yield limitors by correlating bitmap to in-line defect data in an automatic mode, expediting the yield leaming task.Based on the spatial correlation of bitmap data and the information of defects coming from the inline inspections, SmartBitTM provides a pareto where yield loss sources are separated and weighted by impact. SmartBitTM also offers detailed information about the killer defects (defect class, origin, size, kill ratio and more) into a set of reports specially designed to obtain an overall view about the main problems affecting the fab yield. This is the key to fast and efficient yield leaming. These reports are generated automatically using data from the full production of memory-products enhancing the reliability and completeness of the analysis.

show abstract

Advanced yield enhancement methodology for SoCs

Asami

Nasu

Takase

et al.

2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530)

View full text Add to dashboard Cite

A yield simulator utilizing the erfracted critical area and a SoC yield management system has been developed. This system drastically improved accuracy of SoC yield prediction and successfilly extracted the critical areas of all layers of 0.I8pnSoCs in approximately one hour. For yieldprediction, we have thus far extracted critical areas of over I50 SoCs since the 0.I8pn nodes. and performed analysis ofyield-loss factors.There me two factors that aflect the device yield: field defects and product-inherent parametric failure. The yield calculated on the basis of critical areas is a prediction derived considering only field defects. It has been confirmed that SoCs failed to achieve the prediction had product-inherent parametric problems.The new system allows us to determine early in the development cycle whether or not a SoC has any inherent problems. The new system helps to quickly identifv the root cause of a yield loss and reduce the time required to obtain yield improvement.Based on the experience of analyzing many SoC products, we have acquired design-for-manufachrring (DFM) expertise for improving yieldr for new and next-generation products.

show abstract

The 100% yield explanation approach in Lucent Technologies Madrid

Cited by 3 publications

References 11 publications

Methodologies for fast yield ramp with limited engineering resources utilizing Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics

Methodologies for fast yield ramp with limited engineering resources utilizing Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics

SmartBit/sup TM/: bitmap to defect correlation software for yield improvement

Advanced yield enhancement methodology for SoCs

Contact Info

Product

Resources

About