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Many-core architectures integrate a large number of comparatively small processing cores into a single chip. However, the high degree of parallelism increases the run-time resource management complexity and overhead. The employment of dedicated hardware enhancements potentially enables a high quality of the resource management while management overhead is mitigated. To exploit the potential of hardware enhancements, we propose a dedicated infrastructure for run-time resource management on homogeneous MIMD many-core processors. For hardware enhanced resource management, a scalable and cluster-based system architecture is implemented. The resulting architecture (DRACON) utilizes message passing based communication, the dedicated infrastructure and hardware accelerators for resource management. A comprehensive evaluation for DRACON and reference architectures is performed using a transaction level simulation framework and dynamic task management as a use case. As benchmarks, synthetic models and task graph models of real-world applications are applied. The results reveal the limited scalability of classical architectures for resource management on many-cores. It is therefore necessary to apply cluster-based or moderately distributed architectures for many-core resource management. Further, the results demonstrate a significant performance improvement for the DRACON architecture at a number of hundreds of processing cores. Our evaluations show that DRACON generally outperforms software-only run-time management on many-core and achieves a performance improvement of up to 15.21% for single-program and more than 6% for mixed workloads.INDEX TERMS Computer architecture, many-core, dynamic run-time management, dedicated hardware.
Many-core architectures integrate a large number of comparatively small processing cores into a single chip. However, the high degree of parallelism increases the run-time resource management complexity and overhead. The employment of dedicated hardware enhancements potentially enables a high quality of the resource management while management overhead is mitigated. To exploit the potential of hardware enhancements, we propose a dedicated infrastructure for run-time resource management on homogeneous MIMD many-core processors. For hardware enhanced resource management, a scalable and cluster-based system architecture is implemented. The resulting architecture (DRACON) utilizes message passing based communication, the dedicated infrastructure and hardware accelerators for resource management. A comprehensive evaluation for DRACON and reference architectures is performed using a transaction level simulation framework and dynamic task management as a use case. As benchmarks, synthetic models and task graph models of real-world applications are applied. The results reveal the limited scalability of classical architectures for resource management on many-cores. It is therefore necessary to apply cluster-based or moderately distributed architectures for many-core resource management. Further, the results demonstrate a significant performance improvement for the DRACON architecture at a number of hundreds of processing cores. Our evaluations show that DRACON generally outperforms software-only run-time management on many-core and achieves a performance improvement of up to 15.21% for single-program and more than 6% for mixed workloads.INDEX TERMS Computer architecture, many-core, dynamic run-time management, dedicated hardware.
Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.
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