The AIS-5000 parallel processor

Schmitt, Lukas; Wilson, Stephen

doi:10.1109/34.3897

Cited by 64 publications

(13 citation statements)

References 8 publications

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“…This led to an explosion of dierent proposals and implementations [30,25,19,29,27,10] and in some cases to the redesign of previous architectures. Most designs share original characteristics such as the bidimensional mesh interconnection scheme and bit-serial computation, while other ones, such as the Connection Machine [29], have increased the complexity of the interconnection network or widened, as in the CLIP7 [15] or MasPar [24] systems, the data path of the elementary PE.…”

Section: Discussionmentioning

confidence: 98%

“…Most designs share original characteristics such as the bidimensional mesh interconnection scheme and bit-serial computation, while other ones, such as the Connection Machine [29], have increased the complexity of the interconnection network or widened, as in the CLIP7 [15] or MasPar [24] systems, the data path of the elementary PE. Other machines, such as the AIS [27] and the PAPRICA-3 [16,9], have a 1-D interconnection scheme emulating a 2-D mesh organization.…”

Section: Discussionmentioning

confidence: 99%

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Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

2000

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Section: Discussionmentioning

confidence: 98%

Section: Discussionmentioning

confidence: 99%

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

2000

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“…As the architecture is not very different from architectures which are known to perform well on low-level image processing problems (e.g. AIS-5000 [14], LUCAS [5]), this problem area also fits our architecture well.…”

Section: Applicationsmentioning

confidence: 93%

Using FPGAs to implement a reconfigurable highly parallel computer

Linde

Nordström

Taveniku

1993

Lecture Notes in Computer Science

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Abstract. With the arrival of large Field Programmable Gate Arrays (FPGAs) it is possible to build an entire computer using only FPGA and memory. In this paper we share some experience from building a highly parallel computer using this concept. Even if today's FPGAs are of considerable size, each processor must be relatively simple if a highly parallel computer is to be constructed from them. Based on our experience of other parallel computers and thorough studies of the intended applications, we think it is possible to build very powerful and efficient computers using bit-serial processing elements with SIMD (Single Instruction stream, Multiple Data streams) control. A major benefit of using FPGAs is the fact that different architectural variations can easily be tested and evaluated on real applications. In the primary application area, which is artificial neural networks, the gains of extensions like bit-serial multipliers or counters can quickly be found. A concrete implementation of a processor array, using Xilinx FPGAs, is described in this paper. To get efficient usage and high performance with the FPGA circuits signal flow plays an important role. As the current implementation of the Xilinx EDA software does not support that design issue, the signal flow design has to be made by hand. The processing elements are simple and regular which makes it easy to implement them with the XACT Editor. This gives high performance, up to 40-50 MHz.

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“…Generally in image processing applications, the number of PE's is far smaller than the number of image pixels, thus requiring a sort of virtualization of the PA. This is done utilizing an external image memory [40], [47], [51]; the processor array (PA) is loaded from the image memory with a subwindow of the data set; then the computation is performed until a special instruction is reached; finally, the results are stored back again into the external memory. These steps are iterated until all the subwindows have been processed.…”

Section: The Computing Architecturementioning

confidence: 99%

GOLD: a parallel real-time stereo vision system for generic obstacle and lane detection

Bertozzi

Broggi

1998

IEEE Trans. on Image Process.

893

404

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Abstract-This paper describes the Generic Obstacle and Lane Detection system (GOLD), a stereo vision-based hardware and software architecture to be used on moving vehicles to increment road safety. Based on a full-custom massively parallel hardware, it allows to detect both generic obstacles (without constraints on symmetry or shape) and the lane position in a structured environment (with painted lane markings) at a rate of 10 Hz. Thanks to a geometrical transform supported by a specific hardware module, the perspective effect is removed from both left and right stereo images; the left is used to detect lane markings with a series of morphological filters, while both remapped stereo images are used for the detection of free-space in front of the vehicle. The output of the processing is displayed on both an onboard monitor and a control-panel to give visual feedbacks to the driver. The system was tested on the mobile laboratory (MOB-LAB) experimental land vehicle, which was driven for more than 3000 km along extra-urban roads and freeways at speeds up to 80 km/h, and demonstrated its robustness with respect to shadows and changing illumination conditions, different road textures, and vehicle movement.

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The AIS-5000 parallel processor

Cited by 64 publications

References 8 publications

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

Using FPGAs to implement a reconfigurable highly parallel computer

GOLD: a parallel real-time stereo vision system for generic obstacle and lane detection

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