Digital systems blocks are considered. We consider that the functioning of such blocks can be represented as a sequence of functions of a finite alphabet. Digital systems are simulated on the logic level of the signals they exchange with external environment. For a system design debugging by simulation it is necessary to generate the set of tests for applying to the simulated system to verify the correctness of functioning. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.