The automatic generation of functional test vectors for Rambus designs

Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Coverage metrics proposed for measuring the extent of design verification provided by a set of functional simulation vectors should compute statement execution counts (controllability information), and check to see whether effects of possible errors activated by program stimuli can be observed at the circuit outputs (observability information). Unfortunately, the metrics proposed thus far, either do not compute both types of information, or are inefficient, i.e., the overhead of computing the metric is very large.In this paper, we provide the details of an efficient method to compute an Observability-based Code COverage Metric (OC-COM) that can be used while simulating complex HDL designs. This method offers a more accurate assessment of design verification coverage than line coverage, and is significantly more computationally efficient than prior efforts to assess observability information because it breaks up the computation into two phases: Functional simulation of a modified HDL model, followed by analysis of a flowgraph extracted from the HDL model. Commercial HDL simulators can be directly used for the timeconsuming first phase, and the second phase can be performed efficiently using concurrent evaluation techniques.

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“…Design-specific coverage analysis and test generation approaches have been proposed for processors (e.g., [1], [11], [12]). …”

Section: B Hdl Coverage Analysismentioning

confidence: 99%