The Boundary-Scan Handbook

Parker, Kenneth P.

doi:10.1007/978-1-4757-2142-3

Cited by 78 publications

(19 citation statements)

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“…However, up to now, IEEE 1149.4 has not been widely used commercially due to several reasons, such as its IC area concern; its implementation costs; its low measurement frequency bandwidth, which is approximately 1 MHz; and its higher measurement error, which may arise because of the higher impedance of silicon switches [8,22]. With this situation, boundary-scan defect coverage remains unimproved in the same manner as coverage with IEEE 1149.1.…”

Section: Boundary-scan and Current Limitationsmentioning

confidence: 99%

Contactless Testing of Circuit Interconnects

Renbi

Delsing

2015

J Electron Test

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State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 μm and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

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Section: Boundary-scan and Current Limitationsmentioning

confidence: 99%

Contactless Testing of Circuit Interconnects

Renbi

Delsing

2015

J Electron Test

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“…They focus on pre-bond die testing to increase the compound stack yield and propose a "scan island" approach, which is essentially the wrapper technique from IEEE Stds 1149.1 [9,28] and 1500 [5,11] under a different name.…”

Section: Related Prior Workmentioning

confidence: 99%

“…Two successful test access standards for systems built out of pre-defined components are IEEE Std 1149.1 [9,28] for chips on Printed Circuit Boards (PCBs) and IEEE Std 1500 [5,11,22] for embedded cores in System-on-Chips (SOCs). In this section, we briefly describe the similarities and differences of both standards, that serve as a starting point for our proposed 3D-SIC test access architecture.…”

Section: Related Test Access Standardsmentioning

confidence: 99%

“…'JTAG') [9,28]. In order for chips to be compliant to IEEE 1149.1, a small hardware wrapper is added to them.…”

Section: Test Access Architecture For Pcbsmentioning

confidence: 99%

“…Section 4 describes the assumptions and requirements that form the foundation of our 3D DfT architecture. The architecture itself is presented in Section 5; this section also describes the two alternative variants, based on IEEE Std 1149.1 [9,28] and IEEE Std 1500 [5,11]. Section 6 details various implementation aspects of the dielevel wrapper, and in Section 7 we present experimental results.…”

Section: Introductionmentioning

confidence: 99%

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A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level.

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