The Boundary — Scan Handbook

Parker, Kenneth P.

doi:10.1007/978-1-4615-0367-5

Cited by 65 publications

(25 citation statements)

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“…Furthermore, some circuit nodes connecting two or more ball grid array pins may never have surface to test, so it makes boundary scan the only way of quality testing (Ehrenberg, 2007). In current trends, industries are using IEEE 1149.1 boundary scan standard to test the heavily loaded PCB as this method is cost effective and have no need of physical probing (Parker, 1992;Lofstrom, 1996;Hur and Lim, 1994;Lee et al, 1998).…”

Section: Introductionmentioning

confidence: 94%

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Sharma¹,

Sharma

Kaushik

et al. 2011

Circuit World

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Purpose -This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach -The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings -The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.Research limitations/implications -The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications -The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value -Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

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Section: Introductionmentioning

confidence: 94%

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Sharma¹,

Sharma

Kaushik

et al. 2011

Circuit World

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“…This online detection of faults might be obtained through the use of an enlarged boundary scan scheme [14] and test information with extensive coverage to allow the identification of the fault and the reorganization of the ANN without the damaged elements.…”

Section: Fault Tolerance Improvementmentioning

confidence: 99%

FTSET-a software tool for fault tolerance evaluation and improvement

Morgado‐Dias

Borralho

Fontes

et al. 2010

Neural Comput & Applic

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It is commonly assumed that neural networks have a built-in fault tolerance property mainly due to their parallel structure. The international community of neural networks discussed these properties until 1994 and afterward the subject has been mostly ignored. Recently, the subject was again brought to discussion due to the possibility of using neural networks in areas where fault tolerance and graceful degradation properties would be an added value, like medical applications of nano-electronics or space missions. Nevertheless, the evaluation of fault tolerance and graceful degradation characteristics remained difficult because there were no systematic methods or tools that could be easily applied to a given Artificial Neural Networks application. The discussion of models is the first step for sorting ways of developing the fault tolerance capability and for building a tool that can evaluate and improve this characteristic. The present work proposes a fault tolerance model, presents solutions for improving it and introduces the Fault Tolerance Simulation and Evaluation Tool for Artificial Neural Networks that evaluates and improves fault tolerance.

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“…The stack maker might execute post-bond tests on partial and/or complete, not- yet-packaged and/or packaged die stacks; these tests might cover intra-die circuitry (possibly as re-test), as well as the inter-die TSV-based connections [11]. It is assumed that it is a requirement from the stack user that the overall stack product is IEEE 1149.1 [15,16] compliant on its pins, in order to facilitate board-level interconnect testing.…”

Section: Assumptions and Requirementsmentioning

confidence: 99%

“…1500 [13,14] and IEEE Std. 1149.1 [15,16]. Section 4 details various implementation aspects of the die-level wrapper, and in Section 5 we present experimental results.…”

Section: Introductionmentioning

confidence: 99%

3D DfT architecture for pre-bond and post-bond testing

Marinissen

Chi

Verbree

et al. 2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of ThroughSilicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as post-bond stack testing of both partial and complete stacks. The architecture enables on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow flexible optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1500 or IEEE Std 1149.1. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.

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The Boundary — Scan Handbook

Cited by 65 publications

References 0 publications

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

FTSET-a software tool for fault tolerance evaluation and improvement

3D DfT architecture for pre-bond and post-bond testing

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