Al/ZnCdNiTiO2/p-Si diodes with various ratios of active layer were grown onto the p-Si wafer. The functional ZnCdNiTiO2 layer was deposited via sol-gel spin coating method to develop new diodes/structures. Whereas the Ln(I)−V plot shows two linear sections for D1, D2, D3, and D5 structures, D2 and D6 revealed only one linear section in the forward-bias voltages. Therefore, D1, D2, D3, and D5 structures were found to exhibit two-exponential or two-parallel diode behavior in literature. The main electric parameters such as zero-bias barrier height, BH, (Φbo), ideality factor (n), reverse saturation-current (Is, Io)), rectification rate at ±4.5V, series resistance (Rs) and shunt resistance (Rsh) were extracted from the current−voltage (I-V) measurements. The number of surface sates (Nss) and their energy distribution were obtained using forward-bias I-V data by considering the voltage dependence of n and Φbo for each diode. The capacitance / conductance-voltage (C/G−V) plots at 1 MHz were used for extracting some of the other basic electrical parameters. The comparison of all the experimental results suggests that D1 and D3 structures have good performance in terms of lower leakage current, Nss and higher RR and so could be successfully used instead of conventional metal/insulator/semiconductor (MIS) structures.