The case for hardware transactional memory in software packet processing

Abstract

Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and accelerator cores per network node, it is a challenge to support sharing and synchronization across them in a way that is scalable and easy-to-program. In this paper, we focus on parallel/threaded applications that have irregular control-flow and frequently-updated shared state that must be synchronized across threads. However, conventional lock-based synchronization is both difficult to use and also often results in frequent conservative serialization of critical sections. Alternatively, we propose that Transactional memory (TM) is a good match to software packet processing: it both (i) can allow the system to optimistically exploit parallelism between the processing of packets whenever it is safe to do so, and (ii) is easy-to-use for a programmer. With the NetFPGA [1] platform and four network packet processing applications that are threaded and share memory, we evaluate hardware support for TM (HTM) using the reconfigurable FPGA fabric. Relative to NetThreads [2], our two-processor four-way-multithreaded system with conventional lock-based synchronization, we find that adding HTM achieves 6%, 54% and 57% increases in packet throughput for three of four packet processing applications studied, due to reduced conservative serialization.

Configurable Version Management Hardware Transactional Memory for Multi-processor Platform

“…Several other works targeted the implementation of HTM for field programmable gate array (FPGA) platform. ATLAS [14], Real Time Transactional Memory (RTTM) [15] and NetTM [9] were all hardware implementations that were built based on fixed configurations. Their performance are highly dependent on running applications.…”

“…Various architectures proposed by [5,8,9,16] can be categorized into two main aspects: Version Management and Conflict Management [7]. Fig.…”

“…Nonetheless, there are many embedded applications such as network processing that use multiple lightweight Reduced Instruction Set Computer (RISC) or microengines. References [8][9][10] have proposed HTM for embedded systems. The performance of the HTM is dependent on both the configuration and its application.…”

A Stream Reassembly Mechanism Based on DPI

“…Many previously reported methods mainly focus on improving the rule matching algorithms, and/or using FPGA [1], [2] or GPU [3]- [6] for efficient content-matching, and the results show that the ratio of running time used for matching is decreasing with the enhancement of matching performance. Experiments from some other researchers [7] further indicated that when the ratio of the matching time to the overall decrease to 1%, Stream4 (which reassembles streams in previous Snort version) will take on the load of 80% when it is used to assemble the packets.…”